Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	158767788	5156254	0	0
clk_enables_rd_A	158767788	43840	0	0
clk_hints_rd_A	158767788	40335	0	0
extclk_ctrl_rd_A	158767788	50180	0	0
extclk_ctrl_regwen_rd_A	158767788	38263	0	0
jitter_enable_rd_A	158767788	52896	0	0
jitter_regwen_rd_A	158767788	43301	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	5156254	0	0
T1	131814	63855	0	0
T2	0	116831	0	0
T5	52318	0	0	0
T14	0	116780	0	0
T17	0	67411	0	0
T20	1447	0	0	0
T21	1742	0	0	0
T22	1724	0	0	0
T23	907	0	0	0
T24	124138	0	0	0
T25	768	0	0	0
T26	2134	0	0	0
T27	14669	0	0	0
T76	0	125280	0	0
T77	0	81994	0	0
T78	0	247592	0	0
T79	0	79508	0	0
T80	0	63986	0	0
T81	0	96431	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	43840	0	0
T13	269196	0	0	0
T14	337780	0	0	0
T34	15758	3	0	0
T43	868	0	0	0
T76	0	4827	0	0
T84	6959	0	0	0
T85	1607	0	0	0
T86	30008	0	0	0
T87	1474	0	0	0
T88	1924	1	0	0
T148	0	7	0	0
T149	0	2	0	0
T150	0	11	0	0
T151	0	7	0	0
T152	0	5	0	0
T153	0	4	0	0
T154	0	4985	0	0
T155	1109	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	40335	0	0
T13	269196	0	0	0
T14	337780	0	0	0
T34	15758	2	0	0
T43	868	0	0	0
T76	0	4234	0	0
T84	6959	0	0	0
T85	1607	0	0	0
T86	30008	0	0	0
T87	1474	0	0	0
T88	1924	2	0	0
T148	0	9	0	0
T150	0	6	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	5	0	0
T154	0	4812	0	0
T155	1109	0	0	0
T156	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	50180	0	0
T4	26720	0	0	0
T6	6720	0	0	0
T8	1927	56	0	0
T9	914	0	0	0
T22	0	33	0	0
T28	2057	0	0	0
T29	2435	36	0	0
T30	1424	0	0	0
T31	1421	0	0	0
T32	1607	0	0	0
T33	1626	0	0	0
T34	0	18	0	0
T38	0	30	0	0
T58	0	37	0	0
T82	0	7	0	0
T155	0	18	0	0
T157	0	65	0	0
T158	0	22	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	38263	0	0
T15	180361	0	0	0
T47	1400	0	0	0
T76	0	4193	0	0
T90	232485	0	0	0
T94	0	39	0	0
T154	0	4738	0	0
T157	58977	47	0	0
T159	0	12	0	0
T160	0	30	0	0
T161	0	4892	0	0
T162	0	43	0	0
T163	0	3693	0	0
T164	0	3052	0	0
T165	1126	0	0	0
T166	1043	0	0	0
T167	1662	0	0	0
T168	2080	0	0	0
T169	1218	0	0	0
T170	1625	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	52896	0	0
T13	269196	0	0	0
T14	337780	0	0	0
T34	15758	235	0	0
T43	868	0	0	0
T76	0	4870	0	0
T84	6959	0	0	0
T85	1607	0	0	0
T86	30008	0	0	0
T87	1474	0	0	0
T88	1924	125	0	0
T148	0	54	0	0
T149	0	68	0	0
T150	0	239	0	0
T151	0	116	0	0
T152	0	145	0	0
T153	0	147	0	0
T154	0	6249	0	0
T155	1109	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158767788	43301	0	0
T46	0	2212	0	0
T49	30349	0	0	0
T76	436755	4727	0	0
T77	174748	0	0	0
T154	0	5225	0	0
T161	0	5537	0	0
T163	0	4483	0	0
T164	0	3560	0	0
T171	0	3046	0	0
T172	0	2511	0	0
T173	0	4954	0	0
T174	0	1274	0	0
T175	2546	0	0	0
T176	1488	0	0	0
T177	1698	0	0	0
T178	1520	0	0	0
T179	1044	0	0	0
T180	280719	0	0	0
T181	1106	0	0	0