Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T29,T31,T33
1	1	Covered	T8,T29,T31

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	342545021	4131	0	0
g_div2.Div2Whole_A	342545021	5072	0	0
g_div4.Div4Stepped_A	170344734	4039	0	0
g_div4.Div4Whole_A	170344734	4679	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342545021	4131	0	0
T1	0	10	0	0
T4	102607	0	0	0
T6	52999	0	0	0
T8	2848	4	0	0
T9	3251	0	0	0
T20	0	5	0	0
T28	1976	0	0	0
T29	46776	14	0	0
T30	1367	0	0	0
T31	5930	3	0	0
T32	1590	0	0	0
T33	6507	4	0	0
T38	0	5	0	0
T39	0	2	0	0
T40	0	7	0	0
T42	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342545021	5072	0	0
T1	0	19	0	0
T4	102607	0	0	0
T6	52999	0	0	0
T8	2848	6	0	0
T9	3251	0	0	0
T20	0	6	0	0
T28	1976	0	0	0
T29	46776	16	0	0
T30	1367	0	0	0
T31	5930	5	0	0
T32	1590	0	0	0
T33	6507	5	0	0
T38	0	6	0	0
T39	0	3	0	0
T40	0	7	0	0
T42	0	12	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344734	4039	0	0
T1	0	10	0	0
T4	27033	0	0	0
T6	26474	0	0	0
T8	1473	3	0	0
T9	1606	0	0	0
T20	0	5	0	0
T28	969	0	0	0
T29	27117	14	0	0
T30	624	0	0	0
T31	3141	3	0	0
T32	749	0	0	0
T33	3427	4	0	0
T38	0	5	0	0
T39	0	2	0	0
T40	0	7	0	0
T42	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344734	4679	0	0
T1	0	14	0	0
T4	27033	0	0	0
T6	26474	0	0	0
T8	1473	6	0	0
T9	1606	0	0	0
T20	0	6	0	0
T28	969	0	0	0
T29	27117	16	0	0
T30	624	0	0	0
T31	3141	5	0	0
T32	749	0	0	0
T33	3427	5	0	0
T38	0	5	0	0
T39	0	3	0	0
T40	0	7	0	0
T42	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T29,T31,T33
1	1	Covered	T8,T29,T31

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	342545021	4131	0	0
g_div2.Div2Whole_A	342545021	5072	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342545021	4131	0	0
T1	0	10	0	0
T4	102607	0	0	0
T6	52999	0	0	0
T8	2848	4	0	0
T9	3251	0	0	0
T20	0	5	0	0
T28	1976	0	0	0
T29	46776	14	0	0
T30	1367	0	0	0
T31	5930	3	0	0
T32	1590	0	0	0
T33	6507	4	0	0
T38	0	5	0	0
T39	0	2	0	0
T40	0	7	0	0
T42	0	11	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342545021	5072	0	0
T1	0	19	0	0
T4	102607	0	0	0
T6	52999	0	0	0
T8	2848	6	0	0
T9	3251	0	0	0
T20	0	6	0	0
T28	1976	0	0	0
T29	46776	16	0	0
T30	1367	0	0	0
T31	5930	5	0	0
T32	1590	0	0	0
T33	6507	5	0	0
T38	0	6	0	0
T39	0	3	0	0
T40	0	7	0	0
T42	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T29,T31,T33
1	1	Covered	T8,T29,T31

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	170344734	4039	0	0
g_div4.Div4Whole_A	170344734	4679	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344734	4039	0	0
T1	0	10	0	0
T4	27033	0	0	0
T6	26474	0	0	0
T8	1473	3	0	0
T9	1606	0	0	0
T20	0	5	0	0
T28	969	0	0	0
T29	27117	14	0	0
T30	624	0	0	0
T31	3141	3	0	0
T32	749	0	0	0
T33	3427	4	0	0
T38	0	5	0	0
T39	0	2	0	0
T40	0	7	0	0
T42	0	11	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344734	4679	0	0
T1	0	14	0	0
T4	27033	0	0	0
T6	26474	0	0	0
T8	1473	6	0	0
T9	1606	0	0	0
T20	0	6	0	0
T28	969	0	0	0
T29	27117	16	0	0
T30	624	0	0	0
T31	3141	5	0	0
T32	749	0	0	0
T33	3427	5	0	0
T38	0	5	0	0
T39	0	3	0	0
T40	0	7	0	0
T42	0	12	0	0