Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	46513	0	0
CgEnOn_A	2147483647	37268	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	46513	0	0
T2	2770452	0	0	0
T6	385165	3	0	0
T7	21571	9	0	0
T8	18345	3	0	0
T9	20828	4	0	0
T23	42756	13	0	0
T24	457528	0	0	0
T25	13196	0	0	0
T26	8886	0	0	0
T27	58460	0	0	0
T28	12644	7	0	0
T29	305744	3	0	0
T30	8682	17	0	0
T31	38312	3	0	0
T32	10132	49	0	0
T33	42011	3	0	0
T37	0	1	0	0
T47	0	20	0	0
T48	0	10	0	0
T53	8867	0	0	0
T54	22966	0	0	0
T55	9473	0	0	0
T56	44572	0	0	0
T179	0	15	0	0
T182	0	25	0	0
T183	0	15	0	0
T184	0	25	0	0
T185	0	5	0	0
T186	0	5	0	0
T187	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	37268	0	0
T1	0	70	0	0
T2	2223530	92	0	0
T4	143156	0	0	0
T6	159918	0	0	0
T7	3508	6	0	0
T9	0	1	0	0
T13	0	27	0	0
T23	22780	19	0	0
T24	198898	0	0	0
T25	6788	0	0	0
T26	4574	0	0	0
T27	27898	0	0	0
T30	3726	14	0	0
T31	16817	0	0	0
T32	4369	46	0	0
T33	18424	0	0	0
T34	0	44	0	0
T37	10816	4	0	0
T38	3504	0	0	0
T39	6875	0	0	0
T40	8407	0	0	0
T47	0	20	0	0
T48	0	10	0	0
T53	4663	0	0	0
T54	11902	0	0	0
T55	4839	19	0	0
T56	23904	0	0	0
T60	0	32	0	0
T179	0	15	0	0
T182	0	25	0	0
T183	0	15	0	0
T184	0	25	0	0
T185	0	5	0	0
T186	0	5	0	0
T187	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	170344332	129	0	0
CgEnOn_A	170344332	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344332	129	0	0
T2	123501	0	0	0
T23	5033	2	0	0
T24	29904	0	0	0
T25	1485	0	0	0
T26	1002	0	0	0
T27	5294	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	1059	0	0	0
T54	2638	0	0	0
T55	1045	0	0	0
T56	5596	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344332	129	0	0
T2	123501	0	0	0
T23	5033	2	0	0
T24	29904	0	0	0
T25	1485	0	0	0
T26	1002	0	0	0
T27	5294	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	1059	0	0	0
T54	2638	0	0	0
T55	1045	0	0	0
T56	5596	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	85171565	129	0	0
CgEnOn_A	85171565	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	129	0	0
T2	617497	0	0	0
T23	2516	2	0	0
T24	14952	0	0	0
T25	742	0	0	0
T26	501	0	0	0
T27	2645	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	529	0	0	0
T54	1318	0	0	0
T55	523	0	0	0
T56	2796	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	129	0	0
T2	617497	0	0	0
T23	2516	2	0	0
T24	14952	0	0	0
T25	742	0	0	0
T26	501	0	0	0
T27	2645	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	529	0	0	0
T54	1318	0	0	0
T55	523	0	0	0
T56	2796	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342544588	129	0	0
CgEnOn_A	342544588	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342544588	129	0	0
T2	247538	0	0	0
T23	10199	2	0	0
T24	124138	0	0	0
T25	3077	0	0	0
T26	2069	0	0	0
T27	14669	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	2017	0	0	0
T54	5310	0	0	0
T55	2225	0	0	0
T56	9920	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342544588	125	0	0
T2	247538	0	0	0
T23	10199	2	0	0
T24	124138	0	0	0
T25	3077	0	0	0
T26	2069	0	0	0
T27	14669	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	2017	0	0	0
T54	5310	0	0	0
T55	2225	0	0	0
T56	9920	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	367216380	136	0	0
CgEnOn_A	367216380	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	136	0	0
T2	273461	0	0	0
T23	9988	3	0	0
T24	129315	0	0	0
T25	3204	0	0	0
T26	2156	0	0	0
T27	15281	0	0	0
T47	0	4	0	0
T48	0	1	0	0
T53	2102	0	0	0
T54	5532	0	0	0
T55	2317	0	0	0
T56	10334	0	0	0
T179	0	4	0	0
T182	0	4	0	0
T183	0	3	0	0
T184	0	3	0	0
T186	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	134	0	0
T2	273461	0	0	0
T23	9988	3	0	0
T24	129315	0	0	0
T25	3204	0	0	0
T26	2156	0	0	0
T27	15281	0	0	0
T47	0	4	0	0
T48	0	1	0	0
T53	2102	0	0	0
T54	5532	0	0	0
T55	2317	0	0	0
T56	10334	0	0	0
T179	0	4	0	0
T182	0	4	0	0
T183	0	3	0	0
T184	0	3	0	0
T186	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	85171565	129	0	0
CgEnOn_A	85171565	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	129	0	0
T2	617497	0	0	0
T23	2516	2	0	0
T24	14952	0	0	0
T25	742	0	0	0
T26	501	0	0	0
T27	2645	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	529	0	0	0
T54	1318	0	0	0
T55	523	0	0	0
T56	2796	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	129	0	0
T2	617497	0	0	0
T23	2516	2	0	0
T24	14952	0	0	0
T25	742	0	0	0
T26	501	0	0	0
T27	2645	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	529	0	0	0
T54	1318	0	0	0
T55	523	0	0	0
T56	2796	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	367216380	136	0	0
CgEnOn_A	367216380	134	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	136	0	0
T2	273461	0	0	0
T23	9988	3	0	0
T24	129315	0	0	0
T25	3204	0	0	0
T26	2156	0	0	0
T27	15281	0	0	0
T47	0	4	0	0
T48	0	1	0	0
T53	2102	0	0	0
T54	5532	0	0	0
T55	2317	0	0	0
T56	10334	0	0	0
T179	0	4	0	0
T182	0	4	0	0
T183	0	3	0	0
T184	0	3	0	0
T186	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	134	0	0
T2	273461	0	0	0
T23	9988	3	0	0
T24	129315	0	0	0
T25	3204	0	0	0
T26	2156	0	0	0
T27	15281	0	0	0
T47	0	4	0	0
T48	0	1	0	0
T53	2102	0	0	0
T54	5532	0	0	0
T55	2317	0	0	0
T56	10334	0	0	0
T179	0	4	0	0
T182	0	4	0	0
T183	0	3	0	0
T184	0	3	0	0
T186	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Unreachable
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	85171565	129	0	0
CgEnOn_A	85171565	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	129	0	0
T2	617497	0	0	0
T23	2516	2	0	0
T24	14952	0	0	0
T25	742	0	0	0
T26	501	0	0	0
T27	2645	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	529	0	0	0
T54	1318	0	0	0
T55	523	0	0	0
T56	2796	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	129	0	0
T2	617497	0	0	0
T23	2516	2	0	0
T24	14952	0	0	0
T25	742	0	0	0
T26	501	0	0	0
T27	2645	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T53	529	0	0	0
T54	1318	0	0	0
T55	523	0	0	0
T56	2796	0	0	0
T179	0	3	0	0
T182	0	5	0	0
T183	0	3	0	0
T184	0	5	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T47,T48
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	170344332	7611	0	0
CgEnOn_A	170344332	5306	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344332	7611	0	0
T6	26473	1	0	0
T7	1658	1	0	0
T8	1473	1	0	0
T9	1606	1	0	0
T28	969	1	0	0
T29	27116	1	0	0
T30	623	6	0	0
T31	3140	1	0	0
T32	749	17	0	0
T33	3426	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344332	5306	0	0
T1	0	17	0	0
T2	0	24	0	0
T4	27033	0	0	0
T6	26473	0	0	0
T13	0	8	0	0
T23	0	2	0	0
T30	623	5	0	0
T31	3140	0	0	0
T32	749	16	0	0
T33	3426	0	0	0
T34	0	14	0	0
T37	3079	1	0	0
T38	1041	0	0	0
T39	1999	0	0	0
T40	2529	0	0	0
T55	0	6	0	0
T60	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T47,T48
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	85171565	7536	0	0
CgEnOn_A	85171565	5231	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	7536	0	0
T6	13237	1	0	0
T7	829	1	0	0
T8	736	1	0	0
T9	803	1	0	0
T28	484	1	0	0
T29	13555	1	0	0
T30	312	6	0	0
T31	1570	1	0	0
T32	374	16	0	0
T33	1713	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171565	5231	0	0
T1	0	15	0	0
T2	0	22	0	0
T4	13517	0	0	0
T6	13237	0	0	0
T13	0	9	0	0
T23	0	2	0	0
T30	312	5	0	0
T31	1570	0	0	0
T32	374	15	0	0
T33	1713	0	0	0
T34	0	15	0	0
T37	1540	1	0	0
T38	519	0	0	0
T39	999	0	0	0
T40	1264	0	0	0
T55	0	6	0	0
T60	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T47,T48
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	342544588	7640	0	0
CgEnOn_A	342544588	5331	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342544588	7640	0	0
T6	52999	1	0	0
T7	3368	1	0	0
T8	2848	1	0	0
T9	3250	1	0	0
T28	1975	1	0	0
T29	46776	1	0	0
T30	1367	5	0	0
T31	5930	1	0	0
T32	1590	16	0	0
T33	6507	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342544588	5331	0	0
T1	0	17	0	0
T2	0	24	0	0
T4	102606	0	0	0
T6	52999	0	0	0
T13	0	10	0	0
T23	0	2	0	0
T30	1367	4	0	0
T31	5930	0	0	0
T32	1590	15	0	0
T33	6507	0	0	0
T34	0	15	0	0
T37	6197	1	0	0
T38	1944	0	0	0
T39	3877	0	0	0
T40	4614	0	0	0
T55	0	7	0	0
T60	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T47,T48
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	176294074	7585	0	0
CgEnOn_A	176294074	5275	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176294074	7585	0	0
T6	23620	1	0	0
T7	1684	1	0	0
T8	1424	1	0	0
T9	1625	1	0	0
T28	988	1	0	0
T29	23389	1	0	0
T30	684	6	0	0
T31	2964	1	0	0
T32	795	17	0	0
T33	3253	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176294074	5275	0	0
T1	0	18	0	0
T2	0	23	0	0
T4	51305	0	0	0
T6	23620	0	0	0
T13	0	11	0	0
T23	0	2	0	0
T30	684	5	0	0
T31	2964	0	0	0
T32	795	16	0	0
T33	3253	0	0	0
T34	0	14	0	0
T37	3098	1	0	0
T38	972	0	0	0
T39	1938	0	0	0
T40	2307	0	0	0
T55	0	6	0	0
T60	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T7,T9,T28
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	367216380	3814	0	0
CgEnOn_A	367216380	3812	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3814	0	0
T1	0	21	0	0
T2	0	22	0	0
T6	67209	0	0	0
T7	3508	6	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T23	0	3	0	0
T26	0	6	0	0
T28	2057	4	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3812	0	0
T1	0	21	0	0
T2	0	22	0	0
T6	67209	0	0	0
T7	3508	6	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T23	0	3	0	0
T26	0	6	0	0
T28	2057	4	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T7,T9,T28
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	367216380	3851	0	0
CgEnOn_A	367216380	3849	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3851	0	0
T1	0	18	0	0
T2	0	21	0	0
T6	67209	0	0	0
T7	3508	11	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T23	0	3	0	0
T26	0	5	0	0
T28	2057	3	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3849	0	0
T1	0	18	0	0
T2	0	21	0	0
T6	67209	0	0	0
T7	3508	11	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T23	0	3	0	0
T26	0	5	0	0
T28	2057	3	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T7,T28,T37
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	367216380	3778	0	0
CgEnOn_A	367216380	3776	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3778	0	0
T1	0	16	0	0
T2	0	30	0	0
T6	67209	0	0	0
T7	3508	7	0	0
T8	2966	0	0	0
T9	3386	0	0	0
T23	0	3	0	0
T26	0	6	0	0
T28	2057	3	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T59	0	5	0	0
T101	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3776	0	0
T1	0	16	0	0
T2	0	30	0	0
T6	67209	0	0	0
T7	3508	7	0	0
T8	2966	0	0	0
T9	3386	0	0	0
T23	0	3	0	0
T26	0	6	0	0
T28	2057	3	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	2	0	0
T59	0	5	0	0
T101	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T5
1	0	Covered	T7,T9,T28
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	367216380	3781	0	0
CgEnOn_A	367216380	3779	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3781	0	0
T1	0	17	0	0
T2	0	32	0	0
T6	67209	0	0	0
T7	3508	8	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T23	0	3	0	0
T26	0	9	0	0
T28	2057	2	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	367216380	3779	0	0
T1	0	17	0	0
T2	0	32	0	0
T6	67209	0	0	0
T7	3508	8	0	0
T8	2966	0	0	0
T9	3386	1	0	0
T23	0	3	0	0
T26	0	9	0	0
T28	2057	2	0	0
T29	48727	0	0	0
T30	1424	0	0	0
T31	6177	0	0	0
T32	1656	0	0	0
T33	6778	0	0	0
T37	0	1	0	0
T41	0	3	0	0
T59	0	7	0	0