Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T1
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T32,T37
1	0	Covered	T23,T47,T48
1	1	Covered	T7,T8,T9

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	774356217	13644	0	0
GateOpen_A	774356217	13644	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774356217	13644	0	0
T1	0	44	0	0
T2	0	55	0	0
T4	194462	0	0	0
T6	116331	0	0	0
T13	0	30	0	0
T23	0	8	0	0
T30	2987	14	0	0
T31	13606	0	0	0
T32	3509	36	0	0
T33	14902	0	0	0
T34	0	41	0	0
T37	13915	4	0	0
T38	4476	0	0	0
T39	8816	0	0	0
T40	10715	0	0	0
T55	0	16	0	0
T60	0	27	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	774356217	13644	0	0
T1	0	44	0	0
T2	0	55	0	0
T4	194462	0	0	0
T6	116331	0	0	0
T13	0	30	0	0
T23	0	8	0	0
T30	2987	14	0	0
T31	13606	0	0	0
T32	3509	36	0	0
T33	14902	0	0	0
T34	0	41	0	0
T37	13915	4	0	0
T38	4476	0	0	0
T39	8816	0	0	0
T40	10715	0	0	0
T55	0	16	0	0
T60	0	27	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T1
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T32,T37
1	0	Covered	T23,T47,T48
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	85171972	3362	0	0
GateOpen_A	85171972	3362	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171972	3362	0	0
T1	0	11	0	0
T2	0	12	0	0
T4	13517	0	0	0
T6	13237	0	0	0
T13	0	7	0	0
T23	0	2	0	0
T30	312	3	0	0
T31	1570	0	0	0
T32	375	9	0	0
T33	1714	0	0	0
T34	0	11	0	0
T37	1540	1	0	0
T38	519	0	0	0
T39	1000	0	0	0
T40	1265	0	0	0
T55	0	3	0	0
T60	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	85171972	3362	0	0
T1	0	11	0	0
T2	0	12	0	0
T4	13517	0	0	0
T6	13237	0	0	0
T13	0	7	0	0
T23	0	2	0	0
T30	312	3	0	0
T31	1570	0	0	0
T32	375	9	0	0
T33	1714	0	0	0
T34	0	11	0	0
T37	1540	1	0	0
T38	519	0	0	0
T39	1000	0	0	0
T40	1265	0	0	0
T55	0	3	0	0
T60	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T1
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T32,T37
1	0	Covered	T23,T47,T48
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	170344734	3405	0	0
GateOpen_A	170344734	3405	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344734	3405	0	0
T1	0	10	0	0
T2	0	13	0	0
T4	27033	0	0	0
T6	26474	0	0	0
T13	0	6	0	0
T23	0	2	0	0
T30	624	4	0	0
T31	3141	0	0	0
T32	749	8	0	0
T33	3427	0	0	0
T34	0	10	0	0
T37	3080	1	0	0
T38	1041	0	0	0
T39	2000	0	0	0
T40	2529	0	0	0
T55	0	3	0	0
T60	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170344734	3405	0	0
T1	0	10	0	0
T2	0	13	0	0
T4	27033	0	0	0
T6	26474	0	0	0
T13	0	6	0	0
T23	0	2	0	0
T30	624	4	0	0
T31	3141	0	0	0
T32	749	8	0	0
T33	3427	0	0	0
T34	0	10	0	0
T37	3080	1	0	0
T38	1041	0	0	0
T39	2000	0	0	0
T40	2529	0	0	0
T55	0	3	0	0
T60	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T1
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T32,T37
1	0	Covered	T23,T47,T48
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	342545021	3456	0	0
GateOpen_A	342545021	3456	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342545021	3456	0	0
T1	0	10	0	0
T2	0	17	0	0
T4	102607	0	0	0
T6	52999	0	0	0
T13	0	8	0	0
T23	0	2	0	0
T30	1367	3	0	0
T31	5930	0	0	0
T32	1590	9	0	0
T33	6507	0	0	0
T34	0	11	0	0
T37	6197	1	0	0
T38	1944	0	0	0
T39	3877	0	0	0
T40	4614	0	0	0
T55	0	5	0	0
T60	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	342545021	3456	0	0
T1	0	10	0	0
T2	0	17	0	0
T4	102607	0	0	0
T6	52999	0	0	0
T13	0	8	0	0
T23	0	2	0	0
T30	1367	3	0	0
T31	5930	0	0	0
T32	1590	9	0	0
T33	6507	0	0	0
T34	0	11	0	0
T37	6197	1	0	0
T38	1944	0	0	0
T39	3877	0	0	0
T40	4614	0	0	0
T55	0	5	0	0
T60	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T30,T32,T37
0	1	Covered	T30,T32,T1
1	0	Covered	T7,T8,T9

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T32,T37
1	0	Covered	T23,T47,T48
1	1	Covered	T7,T8,T9

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	176294490	3421	0	0
GateOpen_A	176294490	3421	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176294490	3421	0	0
T1	0	13	0	0
T2	0	13	0	0
T4	51305	0	0	0
T6	23621	0	0	0
T13	0	9	0	0
T23	0	2	0	0
T30	684	4	0	0
T31	2965	0	0	0
T32	795	10	0	0
T33	3254	0	0	0
T34	0	9	0	0
T37	3098	1	0	0
T38	972	0	0	0
T39	1939	0	0	0
T40	2307	0	0	0
T55	0	5	0	0
T60	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	176294490	3421	0	0
T1	0	13	0	0
T2	0	13	0	0
T4	51305	0	0	0
T6	23621	0	0	0
T13	0	9	0	0
T23	0	2	0	0
T30	684	4	0	0
T31	2965	0	0	0
T32	795	10	0	0
T33	3254	0	0	0
T34	0	9	0	0
T37	3098	1	0	0
T38	972	0	0	0
T39	1939	0	0	0
T40	2307	0	0	0
T55	0	5	0	0
T60	0	7	0	0