Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	653654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3831263

1

T5

1

T6

22

T7

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1096691	1			T6	19		T7	12		T1	28
values[0x0]	1558120	1			T5	6		T6	21		T7	3
values[0x1]	1830106	1			T5	4		T6	18		T7	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	358789	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4126128

1

T5

1

T6

28

T7

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16951	1			T1	2		T4	8		T2	5
valid_sources[0x01]	17869	1			T1	1		T4	3		T2	1
valid_sources[0x02]	16916	1			T1	1		T4	14		T3	9
valid_sources[0x03]	18687	1			T7	1		T18	2		T4	10
valid_sources[0x04]	16498	1			T7	1		T1	4		T4	9
valid_sources[0x05]	16752	1			T1	1		T4	16		T2	1
valid_sources[0x06]	18466	1			T4	3		T2	4		T125	1
valid_sources[0x07]	17932	1			T1	2		T4	18		T2	1
valid_sources[0x08]	16982	1			T1	1		T4	10		T3	12
valid_sources[0x09]	16999	1			T1	1		T4	2		T2	2
valid_sources[0x0a]	17864	1			T1	1		T4	15		T2	1
valid_sources[0x0b]	16574	1			T1	2		T4	8		T2	16
valid_sources[0x0c]	19796	1			T1	2		T4	4		T2	3
valid_sources[0x0d]	16894	1			T4	8		T24	1		T127	1
valid_sources[0x0e]	19034	1			T1	1		T3	11		T12	170
valid_sources[0x0f]	17417	1			T1	3		T4	15		T2	1
valid_sources[0x10]	18401	1			T1	1		T4	9		T2	2
valid_sources[0x11]	16498	1			T1	5		T4	5		T2	1
valid_sources[0x12]	17828	1			T1	2		T18	1		T4	15
valid_sources[0x13]	17245	1			T1	1		T4	13		T2	3
valid_sources[0x14]	17940	1			T1	2		T4	8		T3	47
valid_sources[0x15]	18304	1			T7	1		T4	4		T3	8
valid_sources[0x16]	17207	1			T4	7		T2	1		T3	17
valid_sources[0x17]	17887	1			T1	3		T4	5		T2	5
valid_sources[0x18]	16259	1			T1	1		T4	13		T2	1
valid_sources[0x19]	18146	1			T1	2		T4	6		T2	2
valid_sources[0x1a]	16630	1			T18	1		T4	14		T3	2
valid_sources[0x1b]	17706	1			T4	3		T3	34		T36	1
valid_sources[0x1c]	17112	1			T5	1		T1	1		T4	8
valid_sources[0x1d]	19165	1			T1	3		T4	8		T23	2
valid_sources[0x1e]	17922	1			T1	1		T4	8		T2	1
valid_sources[0x1f]	18301	1			T1	1		T18	1		T4	7
valid_sources[0x20]	18126	1			T4	11		T3	10		T12	891
valid_sources[0x21]	20197	1			T1	1		T4	6		T2	3
valid_sources[0x22]	17321	1			T1	2		T4	10		T2	2
valid_sources[0x23]	19160	1			T1	1		T4	5		T36	1
valid_sources[0x24]	17071	1			T1	3		T4	6		T3	18
valid_sources[0x25]	16986	1			T1	2		T4	1		T2	6
valid_sources[0x26]	16789	1			T1	1		T18	1		T4	8
valid_sources[0x27]	17293	1			T4	6		T2	4		T126	1
valid_sources[0x28]	16966	1			T1	2		T4	12		T2	1
valid_sources[0x29]	18140	1			T1	1		T4	13		T3	13
valid_sources[0x2a]	16108	1			T1	2		T4	5		T3	10
valid_sources[0x2b]	18077	1			T4	11		T2	3		T22	2
valid_sources[0x2c]	17378	1			T6	29		T18	1		T4	10
valid_sources[0x2d]	18203	1			T1	1		T4	10		T3	15
valid_sources[0x2e]	16873	1			T4	7		T3	9		T122	1
valid_sources[0x2f]	16227	1			T1	3		T4	8		T2	1
valid_sources[0x30]	18278	1			T4	7		T2	3		T3	3
valid_sources[0x31]	16906	1			T4	11		T2	4		T3	20
valid_sources[0x32]	16193	1			T1	2		T4	9		T3	13
valid_sources[0x33]	16802	1			T4	5		T123	2		T12	610
valid_sources[0x34]	17112	1			T1	1		T4	7		T3	5
valid_sources[0x35]	16793	1			T1	5		T4	11		T2	6
valid_sources[0x36]	18820	1			T1	2		T4	4		T2	5
valid_sources[0x37]	17332	1			T1	2		T4	5		T36	1
valid_sources[0x38]	17274	1			T1	2		T4	4		T3	1
valid_sources[0x39]	17670	1			T7	1		T18	1		T4	10
valid_sources[0x3a]	17932	1			T1	3		T4	12		T3	20
valid_sources[0x3b]	16217	1			T1	1		T4	12		T2	6
valid_sources[0x3c]	17358	1			T18	1		T4	11		T3	38
valid_sources[0x3d]	18210	1			T1	3		T4	8		T3	17
valid_sources[0x3e]	17711	1			T4	14		T2	3		T3	12
valid_sources[0x3f]	17163	1			T1	2		T4	5		T2	9
valid_sources[0x40]	18438	1			T1	1		T4	10		T2	4
valid_sources[0x41]	17085	1			T1	2		T4	6		T2	4
valid_sources[0x42]	15771	1			T1	2		T4	7		T3	9
valid_sources[0x43]	18425	1			T1	3		T4	8		T3	2
valid_sources[0x44]	17146	1			T1	1		T4	9		T3	7
valid_sources[0x45]	17578	1			T1	1		T4	12		T2	5
valid_sources[0x46]	17575	1			T1	2		T4	10		T3	2
valid_sources[0x47]	17156	1			T1	1		T4	10		T2	6
valid_sources[0x48]	17783	1			T4	5		T2	1		T12	510
valid_sources[0x49]	18179	1			T1	2		T4	5		T3	3
valid_sources[0x4a]	18493	1			T1	2		T4	5		T2	7
valid_sources[0x4b]	16621	1			T1	3		T4	6		T2	8
valid_sources[0x4c]	17173	1			T4	5		T3	8		T12	56
valid_sources[0x4d]	17384	1			T1	1		T4	7		T2	5
valid_sources[0x4e]	19147	1			T1	1		T4	7		T3	26
valid_sources[0x4f]	17128	1			T4	4		T3	8		T36	1
valid_sources[0x50]	16931	1			T1	2		T4	14		T3	39
valid_sources[0x51]	17447	1			T4	6		T2	1		T3	1
valid_sources[0x52]	17662	1			T1	2		T4	8		T3	14
valid_sources[0x53]	17938	1			T1	2		T4	11		T2	1
valid_sources[0x54]	18116	1			T1	1		T4	9		T2	4
valid_sources[0x55]	17573	1			T5	1		T7	1		T4	10
valid_sources[0x56]	16706	1			T4	5		T2	3		T3	39
valid_sources[0x57]	17299	1			T1	2		T4	12		T2	1
valid_sources[0x58]	15757	1			T4	2		T2	2		T3	5
valid_sources[0x59]	16408	1			T1	1		T4	8		T2	3
valid_sources[0x5a]	16890	1			T1	1		T18	1		T4	5
valid_sources[0x5b]	17611	1			T1	3		T4	4		T2	1
valid_sources[0x5c]	18133	1			T1	3		T4	6		T2	4
valid_sources[0x5d]	15898	1			T5	1		T18	1		T4	10
valid_sources[0x5e]	16754	1			T1	2		T4	2		T2	1
valid_sources[0x5f]	19074	1			T1	1		T4	5		T2	4
valid_sources[0x60]	18009	1			T1	1		T4	10		T2	4
valid_sources[0x61]	16626	1			T6	24		T4	8		T2	4
valid_sources[0x62]	19496	1			T1	3		T4	11		T2	4
valid_sources[0x63]	16826	1			T7	1		T4	5		T2	3
valid_sources[0x64]	17434	1			T1	3		T4	5		T2	1
valid_sources[0x65]	16427	1			T5	1		T1	1		T4	3
valid_sources[0x66]	18491	1			T1	2		T18	2		T4	3
valid_sources[0x67]	17407	1			T1	1		T4	4		T2	1
valid_sources[0x68]	19047	1			T1	1		T4	11		T2	9
valid_sources[0x69]	17584	1			T5	2		T4	7		T3	15
valid_sources[0x6a]	19296	1			T1	4		T4	4		T2	1
valid_sources[0x6b]	17208	1			T1	2		T4	8		T3	19
valid_sources[0x6c]	17645	1			T1	1		T4	10		T2	1
valid_sources[0x6d]	17001	1			T4	8		T2	4		T3	6
valid_sources[0x6e]	16885	1			T1	1		T4	10		T2	2
valid_sources[0x6f]	17127	1			T1	1		T4	10		T2	2
valid_sources[0x70]	17446	1			T1	1		T18	2		T4	7
valid_sources[0x71]	16308	1			T1	2		T4	8		T2	3
valid_sources[0x72]	18483	1			T1	2		T4	10		T2	1
valid_sources[0x73]	17293	1			T1	3		T4	13		T2	4
valid_sources[0x74]	17272	1			T7	1		T4	9		T2	2
valid_sources[0x75]	18772	1			T1	2		T4	9		T3	3
valid_sources[0x76]	16985	1			T1	3		T4	14		T2	2
valid_sources[0x77]	16790	1			T4	6		T2	1		T3	13
valid_sources[0x78]	17613	1			T1	3		T4	11		T2	4
valid_sources[0x79]	17052	1			T4	6		T3	18		T23	3
valid_sources[0x7a]	16149	1			T7	1		T1	1		T4	6
valid_sources[0x7b]	17367	1			T1	1		T4	4		T3	4
valid_sources[0x7c]	17038	1			T1	1		T4	3		T2	4
valid_sources[0x7d]	18833	1			T1	2		T4	5		T2	8
valid_sources[0x7e]	17845	1			T1	5		T4	4		T2	1
valid_sources[0x7f]	16453	1			T4	5		T127	2		T12	108
valid_sources[0x80]	16525	1			T1	3		T4	5		T2	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

964021

1

T6

10

T7

7

T1

11

values[0x0]

all_enables

biggest_size

1458449

1

T5

1

T6

8

T1

105

values[0x1]

all_enables

biggest_size

1408793

1

T6

4

T1

56

T4

256