Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	847946235	83534	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	847946235	83534	0	0
T1	270385	53	0	0
T2	314125	93	0	0
T3	1218630	267	0	0
T4	1039055	0	0	0
T11	0	877	0	0
T12	0	1211	0	0
T13	0	85	0	0
T14	0	242	0	0
T15	0	86	0	0
T16	0	1470	0	0
T17	0	85	0	0
T18	5850	0	0	0
T19	7525	0	0	0
T20	5720	0	0	0
T21	12145	0	0	0
T22	7525	0	0	0
T23	12790	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169589247	12206	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	12206	0	0
T1	54077	8	0	0
T2	62825	15	0	0
T3	243726	42	0	0
T4	207811	0	0	0
T11	0	118	0	0
T12	0	192	0	0
T13	0	15	0	0
T14	0	39	0	0
T15	0	14	0	0
T16	0	214	0	0
T17	0	15	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	0	0	0
T21	2429	0	0	0
T22	1505	0	0	0
T23	2558	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169589247	16722	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	16722	0	0
T1	54077	10	0	0
T2	62825	19	0	0
T3	243726	54	0	0
T4	207811	0	0	0
T11	0	179	0	0
T12	0	247	0	0
T13	0	17	0	0
T14	0	49	0	0
T15	0	18	0	0
T16	0	296	0	0
T17	0	17	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	0	0	0
T21	2429	0	0	0
T22	1505	0	0	0
T23	2558	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169589247	25646	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	25646	0	0
T1	54077	16	0	0
T2	62825	25	0	0
T3	243726	76	0	0
T4	207811	0	0	0
T11	0	294	0	0
T12	0	337	0	0
T13	0	21	0	0
T14	0	67	0	0
T15	0	23	0	0
T16	0	454	0	0
T17	0	21	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	0	0	0
T21	2429	0	0	0
T22	1505	0	0	0
T23	2558	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169589247	12218	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	12218	0	0
T1	54077	8	0	0
T2	62825	15	0	0
T3	243726	41	0	0
T4	207811	0	0	0
T11	0	111	0	0
T12	0	190	0	0
T13	0	15	0	0
T14	0	38	0	0
T15	0	14	0	0
T16	0	210	0	0
T17	0	15	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	0	0	0
T21	2429	0	0	0
T22	1505	0	0	0
T23	2558	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	169589247	16742	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	16742	0	0
T1	54077	11	0	0
T2	62825	19	0	0
T3	243726	54	0	0
T4	207811	0	0	0
T11	0	175	0	0
T12	0	245	0	0
T13	0	17	0	0
T14	0	49	0	0
T15	0	17	0	0
T16	0	296	0	0
T17	0	17	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	0	0	0
T21	2429	0	0	0
T22	1505	0	0	0
T23	2558	0	0	0