Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T3,T11

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	169589247	166949391	0	0
AllClkBypReqTrue_A	169589247	144459	0	0
IoClkBypReqFalse_A	169589247	166863414	0	2415
IoClkBypReqTrue_A	169589247	225804	0	0
LcClkBypAckFalse_A	169589247	166963542	0	0
LcClkBypAckTrue_A	169589247	130308	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	166949391	0	0
T1	54077	54025	0	0
T2	62825	62786	0	0
T4	207811	206974	0	0
T5	756	739	0	0
T6	2510	2187	0	0
T7	1655	1423	0	0
T18	1170	1161	0	0
T19	1505	1338	0	0
T20	1144	1099	0	0
T21	2429	2385	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	144459	0	0
T1	54077	0	0	0
T2	62825	0	0	0
T3	0	203	0	0
T4	207811	358	0	0
T6	2510	273	0	0
T7	1655	0	0	0
T11	0	929	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	17	0	0
T21	2429	0	0	0
T22	1505	122	0	0
T121	0	54	0	0
T122	0	106	0	0
T123	0	198	0	0
T124	0	31	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	166863414	0	2415
T1	54077	54023	0	3
T2	62825	62784	0	3
T4	207811	206647	0	3
T5	756	737	0	3
T6	2510	1969	0	3
T7	1655	1421	0	3
T18	1170	1159	0	3
T19	1505	1336	0	3
T20	1144	1079	0	3
T21	2429	2383	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	225804	0	0
T1	54077	0	0	0
T2	62825	0	0	0
T3	0	233	0	0
T4	207811	661	0	0
T6	2510	489	0	0
T7	1655	0	0	0
T11	0	1103	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	35	0	0
T21	2429	0	0	0
T22	1505	239	0	0
T121	0	28	0	0
T122	0	148	0	0
T125	0	245	0	0
T126	0	269	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	166963542	0	0
T1	54077	54025	0	0
T2	62825	62786	0	0
T4	207811	206950	0	0
T5	756	739	0	0
T6	2510	2293	0	0
T7	1655	1423	0	0
T18	1170	1161	0	0
T19	1505	1338	0	0
T20	1144	1087	0	0
T21	2429	2385	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	130308	0	0
T1	54077	0	0	0
T2	62825	0	0	0
T3	0	172	0	0
T4	207811	382	0	0
T6	2510	167	0	0
T7	1655	0	0	0
T11	0	793	0	0
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	29	0	0
T21	2429	0	0	0
T22	1505	156	0	0
T121	0	23	0	0
T122	0	110	0	0
T125	0	133	0	0
T126	0	141	0	0