Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	16700	0	0
TransStop_A	2147483647	8600	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16700	0	0
T1	772528	0	0	0
T2	1005216	0	0	0
T3	3918144	120	0	0
T4	3084988	38	0	0
T7	6896	6	0	0
T11	0	88	0	0
T12	0	254	0	0
T18	93712	10	0	0
T19	6008	0	0	0
T20	19076	0	0	0
T21	18692	52	0	0
T22	12048	0	0	0
T23	0	25	0	0
T36	0	4	0	0
T127	0	13	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	8600	0	0
T1	579396	0	0	0
T2	1005216	0	0	0
T3	3918144	78	0	0
T4	3084988	24	0	0
T7	5172	4	0	0
T11	0	45	0	0
T12	0	113	0	0
T18	70284	2	0	0
T19	4506	0	0	0
T20	19076	0	0	0
T21	18692	30	0	0
T22	12048	0	0	0
T23	5445	9	0	0
T29	4289	0	0	0
T36	5995	4	0	0
T71	0	2	0	0
T72	0	2	0	0
T125	30681	0	0	0
T127	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	551572758	4182	0	0
TransStop_A	551572758	2138	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	4182	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	31	0	0
T4	771247	9	0	0
T7	1724	1	0	0
T11	0	20	0	0
T12	0	62	0	0
T18	23428	4	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	15	0	0
T22	3012	0	0	0
T23	0	5	0	0
T36	0	1	0	0
T127	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	2138	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	18	0	0
T4	771247	6	0	0
T7	1724	1	0	0
T11	0	9	0	0
T12	0	29	0	0
T18	23428	1	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	9	0	0
T22	3012	0	0	0
T23	0	1	0	0
T36	0	1	0	0
T127	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	551572758	4168	0	0
TransStop_A	551572758	2113	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	4168	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	35	0	0
T4	771247	8	0	0
T7	1724	1	0	0
T11	0	24	0	0
T12	0	70	0	0
T18	23428	1	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	14	0	0
T22	3012	0	0	0
T23	0	8	0	0
T36	0	1	0	0
T127	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	2113	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	22	0	0
T4	771247	4	0	0
T7	1724	1	0	0
T11	0	14	0	0
T12	0	29	0	0
T18	23428	0	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	8	0	0
T22	3012	0	0	0
T23	0	3	0	0
T36	0	1	0	0
T71	0	1	0	0
T127	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	551572758	4162	0	0
TransStop_A	551572758	2150	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	4162	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	31	0	0
T4	771247	13	0	0
T7	1724	1	0	0
T11	0	20	0	0
T12	0	62	0	0
T18	23428	1	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	11	0	0
T22	3012	0	0	0
T23	0	4	0	0
T36	0	1	0	0
T127	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	2150	0	0
T2	251304	0	0	0
T3	979536	21	0	0
T4	771247	8	0	0
T11	0	9	0	0
T12	0	26	0	0
T20	4769	0	0	0
T21	4673	6	0	0
T22	3012	0	0	0
T23	5445	2	0	0
T29	4289	0	0	0
T36	5995	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T125	30681	0	0	0
T127	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	551572758	4188	0	0
TransStop_A	551572758	2199	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	4188	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	23	0	0
T4	771247	8	0	0
T7	1724	3	0	0
T11	0	24	0	0
T12	0	60	0	0
T18	23428	4	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	12	0	0
T22	3012	0	0	0
T23	0	8	0	0
T36	0	1	0	0
T127	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572758	2199	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	17	0	0
T4	771247	6	0	0
T7	1724	2	0	0
T11	0	13	0	0
T12	0	29	0	0
T18	23428	1	0	0
T19	1502	0	0	0
T20	4769	0	0	0
T21	4673	7	0	0
T22	3012	0	0	0
T23	0	3	0	0
T36	0	1	0	0
T127	0	1	0	0