Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	169589247	24645284	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169589247	24645284	0	59
T1	54077	4370	0	1
T2	62825	6947	0	1
T3	243726	19979	0	0
T4	207811	1423	0	0
T11	0	108893	0	0
T12	0	81357	0	0
T13	0	3568	0	1
T14	0	15953	0	1
T15	0	433341	0	0
T16	0	118081	0	0
T17	0	0	0	1
T18	1170	0	0	0
T19	1505	0	0	0
T20	1144	0	0	0
T21	2429	0	0	0
T22	1505	0	0	0
T23	2558	0	0	0
T26	0	0	0	1
T28	0	0	0	1
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1