Module Definition
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Module : clkmgr_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_csr_assert 100.00 100.00



Module Instance : tb.dut.clkmgr_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : clkmgr_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 7 7 100.00 7 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 7 7 100.00 7 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 170484393 5584901 0 0
clk_enables_rd_A 170484393 56511 0 0
clk_hints_rd_A 170484393 47981 0 0
extclk_ctrl_rd_A 170484393 64757 0 0
extclk_ctrl_regwen_rd_A 170484393 49308 0 0
jitter_enable_rd_A 170484393 70559 0 0
jitter_regwen_rd_A 170484393 54754 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 5584901 0 0
T12 223666 106744 0 0
T13 17319 0 0 0
T15 0 50309 0 0
T16 0 114022 0 0
T27 8840 0 0 0
T34 1705 0 0 0
T60 0 43724 0 0
T61 0 145973 0 0
T62 0 75572 0 0
T63 0 106375 0 0
T64 0 213428 0 0
T65 0 72339 0 0
T66 0 49765 0 0
T67 780 0 0 0
T68 1141 0 0 0
T69 1276 0 0 0
T70 1520 0 0 0
T71 1804 0 0 0
T72 1459 0 0 0

clk_enables_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 56511 0 0
T11 820733 9 0 0
T16 0 4390 0 0
T24 17585 0 0 0
T25 7924 0 0 0
T30 1467 0 0 0
T60 0 945 0 0
T61 0 5705 0 0
T92 0 5 0 0
T121 1242 0 0 0
T122 1651 0 0 0
T123 1695 0 0 0
T124 1097 0 0 0
T126 2068 0 0 0
T127 1502 0 0 0
T148 0 5 0 0
T149 0 1 0 0
T150 0 1 0 0
T151 0 2 0 0
T152 0 5831 0 0

clk_hints_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 47981 0 0
T11 820733 9 0 0
T16 0 3584 0 0
T24 17585 0 0 0
T25 7924 0 0 0
T30 1467 0 0 0
T60 0 772 0 0
T61 0 4580 0 0
T121 1242 0 0 0
T122 1651 0 0 0
T123 1695 0 0 0
T124 1097 0 0 0
T126 2068 0 0 0
T127 1502 0 0 0
T149 0 5 0 0
T151 0 1 0 0
T152 0 4707 0 0
T153 0 4 0 0
T154 0 1 0 0
T155 0 3797 0 0

extclk_ctrl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 64757 0 0
T1 54077 0 0 0
T2 62825 0 0 0
T4 207811 0 0 0
T6 2510 58 0 0
T7 1655 0 0 0
T11 0 129 0 0
T16 0 4986 0 0
T18 1170 0 0 0
T19 1505 0 0 0
T20 1144 0 0 0
T21 2429 0 0 0
T22 1505 0 0 0
T60 0 942 0 0
T61 0 5787 0 0
T156 0 3 0 0
T157 0 21 0 0
T158 0 22 0 0
T159 0 43 0 0
T160 0 12 0 0

extclk_ctrl_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 49308 0 0
T16 385756 3950 0 0
T26 19502 0 0 0
T60 0 817 0 0
T61 0 4771 0 0
T119 0 20 0 0
T152 0 4682 0 0
T157 1878 0 0 0
T161 0 26 0 0
T162 0 9 0 0
T163 0 9 0 0
T164 0 24 0 0
T165 0 31 0 0
T166 1991 0 0 0
T167 1054 0 0 0
T168 1352 0 0 0
T169 1581 0 0 0
T170 1388 0 0 0
T171 812 0 0 0
T172 1663 0 0 0

jitter_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 70559 0 0
T11 820733 415 0 0
T16 0 5719 0 0
T24 17585 0 0 0
T25 7924 0 0 0
T30 1467 0 0 0
T60 0 1221 0 0
T61 0 6354 0 0
T92 0 70 0 0
T121 1242 0 0 0
T122 1651 0 0 0
T123 1695 0 0 0
T124 1097 0 0 0
T126 2068 0 0 0
T127 1502 0 0 0
T148 0 101 0 0
T149 0 124 0 0
T150 0 120 0 0
T151 0 123 0 0
T153 0 64 0 0

jitter_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 170484393 54754 0 0
T16 385756 4289 0 0
T26 19502 0 0 0
T31 0 7702 0 0
T60 0 792 0 0
T61 0 5885 0 0
T152 0 5287 0 0
T155 0 4574 0 0
T157 1878 0 0 0
T166 1991 0 0 0
T167 1054 0 0 0
T168 1352 0 0 0
T169 1581 0 0 0
T170 1388 0 0 0
T171 812 0 0 0
T172 1663 0 0 0
T173 0 2947 0 0
T174 0 1708 0 0
T175 0 3920 0 0
T176 0 3711 0 0

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