Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	50957	0	0
CgEnOn_A	2147483647	41697	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	50957	0	0
T1	1189593	3	0	0
T2	2593323	3	0	0
T3	7798706	31	0	0
T4	7471426	144	0	0
T5	13569	3	0	0
T6	22208	3	0	0
T7	10540	4	0	0
T18	144266	7	0	0
T19	15162	29	0	0
T20	56827	3	0	0
T21	48164	18	0	0
T22	25107	0	0	0
T23	22550	5	0	0
T34	0	35	0	0
T35	0	25	0	0
T36	24840	0	0	0
T125	131214	0	0	0
T166	0	20	0	0
T171	0	10	0	0
T177	0	20	0	0
T178	0	10	0	0
T179	0	20	0	0
T180	0	15	0	0
T181	0	30	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41697	0	0
T1	772528	0	0	0
T2	2593323	0	0	0
T3	9763356	94	0	0
T4	7471426	108	0	0
T7	6896	1	0	0
T11	0	96	0	0
T12	0	399	0	0
T18	93712	4	0	0
T19	15162	26	0	0
T20	56827	0	0	0
T21	48164	15	0	0
T22	31934	0	0	0
T23	34250	0	0	0
T34	0	56	0	0
T35	0	25	0	0
T36	37729	4	0	0
T67	0	12	0	0
T68	0	39	0	0
T69	0	13	0	0
T125	199634	0	0	0
T166	0	20	0	0
T171	0	10	0	0
T177	0	20	0	0
T178	0	10	0	0
T179	0	20	0	0
T180	0	15	0	0
T181	0	30	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	258454040	179	0	0
CgEnOn_A	258454040	179	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258454040	179	0	0
T2	120596	0	0	0
T3	427029	0	0	0
T4	307287	0	0	0
T19	656	3	0	0
T20	4192	0	0	0
T21	2230	0	0	0
T22	1660	0	0	0
T23	2573	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	2838	0	0	0
T125	16162	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258454040	179	0	0
T2	120596	0	0	0
T3	427029	0	0	0
T4	307287	0	0	0
T19	656	3	0	0
T20	4192	0	0	0
T21	2230	0	0	0
T22	1660	0	0	0
T23	2573	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	2838	0	0	0
T125	16162	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129226340	179	0	0
CgEnOn_A	129226340	179	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	179	0	0
T2	60298	0	0	0
T3	213512	0	0	0
T4	153643	0	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	1419	0	0	0
T125	8080	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	179	0	0
T2	60298	0	0	0
T3	213512	0	0	0
T4	153643	0	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	1419	0	0	0
T125	8080	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	518079282	179	0	0
CgEnOn_A	518079282	171	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518079282	179	0	0
T2	241244	0	0	0
T3	853925	0	0	0
T4	613657	0	0	0
T19	1419	3	0	0
T20	4578	0	0	0
T21	4485	0	0	0
T22	2891	0	0	0
T23	5226	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	5755	0	0	0
T125	29452	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518079282	171	0	0
T2	241244	0	0	0
T3	853925	0	0	0
T4	613657	0	0	0
T19	1419	3	0	0
T20	4578	0	0	0
T21	4485	0	0	0
T22	2891	0	0	0
T23	5226	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	5755	0	0	0
T125	29452	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	551572297	150	0	0
CgEnOn_A	551572297	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	150	0	0
T2	251304	0	0	0
T3	979536	0	0	0
T4	771247	0	0	0
T12	0	1	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	0	0	0
T22	3011	0	0	0
T23	5445	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	5995	0	0	0
T125	30680	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	147	0	0
T2	251304	0	0	0
T3	979536	0	0	0
T4	771247	0	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	0	0	0
T22	3011	0	0	0
T23	5445	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	5995	0	0	0
T125	30680	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	0	6	0	0
T181	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129226340	179	0	0
CgEnOn_A	129226340	179	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	179	0	0
T2	60298	0	0	0
T3	213512	0	0	0
T4	153643	0	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	1419	0	0	0
T125	8080	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	179	0	0
T2	60298	0	0	0
T3	213512	0	0	0
T4	153643	0	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	1419	0	0	0
T125	8080	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	551572297	150	0	0
CgEnOn_A	551572297	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	150	0	0
T2	251304	0	0	0
T3	979536	0	0	0
T4	771247	0	0	0
T12	0	1	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	0	0	0
T22	3011	0	0	0
T23	5445	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	5995	0	0	0
T125	30680	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	147	0	0
T2	251304	0	0	0
T3	979536	0	0	0
T4	771247	0	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	0	0	0
T22	3011	0	0	0
T23	5445	0	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	5995	0	0	0
T125	30680	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	1	0	0
T179	0	3	0	0
T180	0	6	0	0
T181	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129226340	179	0	0
CgEnOn_A	129226340	179	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	179	0	0
T2	60298	0	0	0
T3	213512	0	0	0
T4	153643	0	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	1419	0	0	0
T125	8080	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	179	0	0
T2	60298	0	0	0
T3	213512	0	0	0
T4	153643	0	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T35	0	5	0	0
T36	1419	0	0	0
T125	8080	0	0	0
T166	0	4	0	0
T171	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	3	0	0
T181	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	258454040	8102	0	0
CgEnOn_A	258454040	5798	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258454040	8102	0	0
T1	92640	1	0	0
T2	120596	1	0	0
T4	307287	44	0	0
T5	2998	1	0	0
T6	5165	1	0	0
T7	774	1	0	0
T18	11212	1	0	0
T19	656	4	0	0
T20	4192	1	0	0
T21	2230	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258454040	5798	0	0
T2	120596	0	0	0
T3	427029	21	0	0
T4	307287	32	0	0
T11	0	25	0	0
T12	0	135	0	0
T19	656	3	0	0
T20	4192	0	0	0
T21	2230	0	0	0
T22	1660	0	0	0
T23	2573	0	0	0
T34	0	7	0	0
T36	2838	1	0	0
T67	0	4	0	0
T68	0	14	0	0
T69	0	4	0	0
T125	16162	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	129226340	8078	0	0
CgEnOn_A	129226340	5774	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	8078	0	0
T1	46320	1	0	0
T2	60298	1	0	0
T4	153643	46	0	0
T5	1499	1	0	0
T6	2582	1	0	0
T7	387	1	0	0
T18	5606	1	0	0
T19	328	4	0	0
T20	2096	1	0	0
T21	1115	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226340	5774	0	0
T2	60298	0	0	0
T3	213512	21	0	0
T4	153643	34	0	0
T11	0	24	0	0
T12	0	135	0	0
T19	328	3	0	0
T20	2096	0	0	0
T21	1115	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T36	1419	1	0	0
T67	0	3	0	0
T68	0	11	0	0
T69	0	5	0	0
T125	8080	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	518079282	8159	0	0
CgEnOn_A	518079282	5847	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518079282	8159	0	0
T1	185401	1	0	0
T2	241244	1	0	0
T4	613657	45	0	0
T5	6048	1	0	0
T6	9641	1	0	0
T7	1655	1	0	0
T18	22490	1	0	0
T19	1419	4	0	0
T20	4578	1	0	0
T21	4485	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518079282	5847	0	0
T2	241244	0	0	0
T3	853925	21	0	0
T4	613657	33	0	0
T11	0	27	0	0
T12	0	129	0	0
T19	1419	3	0	0
T20	4578	0	0	0
T21	4485	0	0	0
T22	2891	0	0	0
T23	5226	0	0	0
T34	0	7	0	0
T36	5755	1	0	0
T67	0	5	0	0
T68	0	14	0	0
T69	0	4	0	0
T125	29452	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T34,T35
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	264578890	8123	0	0
CgEnOn_A	264578890	5809	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264578890	8123	0	0
T1	92704	1	0	0
T2	120627	1	0	0
T4	387484	45	0	0
T5	3024	1	0	0
T6	4820	1	0	0
T7	828	1	0	0
T18	11246	1	0	0
T19	694	2	0	0
T20	2289	1	0	0
T21	2242	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264578890	5809	0	0
T2	120627	0	0	0
T3	470184	19	0	0
T4	387484	33	0	0
T11	0	25	0	0
T12	0	123	0	0
T19	694	1	0	0
T20	2289	0	0	0
T21	2242	0	0	0
T22	1446	0	0	0
T23	2614	0	0	0
T34	0	6	0	0
T36	2877	1	0	0
T67	0	3	0	0
T68	0	14	0	0
T69	0	4	0	0
T125	14726	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Covered	T7,T18,T4
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	551572297	4332	0	0
CgEnOn_A	551572297	4329	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4332	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	31	0	0
T4	771247	9	0	0
T7	1724	1	0	0
T11	0	20	0	0
T18	23428	4	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	15	0	0
T22	3011	0	0	0
T23	0	5	0	0
T36	0	1	0	0
T127	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4329	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	31	0	0
T4	771247	9	0	0
T7	1724	1	0	0
T11	0	20	0	0
T18	23428	4	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	15	0	0
T22	3011	0	0	0
T23	0	5	0	0
T36	0	1	0	0
T127	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Covered	T7,T18,T4
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	551572297	4318	0	0
CgEnOn_A	551572297	4315	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4318	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	35	0	0
T4	771247	8	0	0
T7	1724	1	0	0
T11	0	24	0	0
T18	23428	1	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	14	0	0
T22	3011	0	0	0
T23	0	8	0	0
T36	0	1	0	0
T127	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4315	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	35	0	0
T4	771247	8	0	0
T7	1724	1	0	0
T11	0	24	0	0
T18	23428	1	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	14	0	0
T22	3011	0	0	0
T23	0	8	0	0
T36	0	1	0	0
T127	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Covered	T7,T18,T4
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	551572297	4312	0	0
CgEnOn_A	551572297	4309	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4312	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	31	0	0
T4	771247	13	0	0
T7	1724	1	0	0
T11	0	20	0	0
T18	23428	1	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	11	0	0
T22	3011	0	0	0
T23	0	4	0	0
T36	0	1	0	0
T127	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4309	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	31	0	0
T4	771247	13	0	0
T7	1724	1	0	0
T11	0	20	0	0
T18	23428	1	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	11	0	0
T22	3011	0	0	0
T23	0	4	0	0
T36	0	1	0	0
T127	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T4,T3
1	0	Covered	T7,T18,T4
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	551572297	4338	0	0
CgEnOn_A	551572297	4335	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4338	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	23	0	0
T4	771247	8	0	0
T7	1724	3	0	0
T11	0	24	0	0
T18	23428	4	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	12	0	0
T22	3011	0	0	0
T23	0	8	0	0
T36	0	1	0	0
T127	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	551572297	4335	0	0
T1	193132	0	0	0
T2	251304	0	0	0
T3	979536	23	0	0
T4	771247	8	0	0
T7	1724	3	0	0
T11	0	24	0	0
T18	23428	4	0	0
T19	1501	2	0	0
T20	4769	0	0	0
T21	4672	12	0	0
T22	3011	0	0	0
T23	0	8	0	0
T36	0	1	0	0
T127	0	2	0	0