Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T4,T3
0	1	Covered	T4,T3,T11
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T36
1	0	Covered	T19,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1170340237	15078	0	0
GateOpen_A	1170340237	15078	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170340237	15078	0	0
T2	542766	0	0	0
T3	1964653	54	0	0
T4	1462074	84	0	0
T11	0	79	0	0
T12	0	298	0	0
T19	3100	10	0	0
T20	13158	0	0	0
T21	10076	0	0	0
T22	6829	0	0	0
T23	11702	0	0	0
T34	0	27	0	0
T36	12890	4	0	0
T67	0	5	0	0
T68	0	37	0	0
T69	0	15	0	0
T125	68423	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1170340237	15078	0	0
T2	542766	0	0	0
T3	1964653	54	0	0
T4	1462074	84	0	0
T11	0	79	0	0
T12	0	298	0	0
T19	3100	10	0	0
T20	13158	0	0	0
T21	10076	0	0	0
T22	6829	0	0	0
T23	11702	0	0	0
T34	0	27	0	0
T36	12890	4	0	0
T67	0	5	0	0
T68	0	37	0	0
T69	0	15	0	0
T125	68423	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T4,T3
0	1	Covered	T4,T3,T11
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T36
1	0	Covered	T19,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	129226766	3757	0	0
GateOpen_A	129226766	3757	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226766	3757	0	0
T2	60298	0	0	0
T3	213513	12	0	0
T4	153644	21	0	0
T11	0	20	0	0
T12	0	73	0	0
T19	329	3	0	0
T20	2096	0	0	0
T21	1116	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T36	1419	1	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	5	0	0
T125	8081	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	129226766	3757	0	0
T2	60298	0	0	0
T3	213513	12	0	0
T4	153644	21	0	0
T11	0	20	0	0
T12	0	73	0	0
T19	329	3	0	0
T20	2096	0	0	0
T21	1116	0	0	0
T22	830	0	0	0
T23	1287	0	0	0
T34	0	7	0	0
T36	1419	1	0	0
T67	0	1	0	0
T68	0	7	0	0
T69	0	5	0	0
T125	8081	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T4,T3
0	1	Covered	T4,T3,T11
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T36
1	0	Covered	T19,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	258454443	3753	0	0
GateOpen_A	258454443	3753	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258454443	3753	0	0
T2	120596	0	0	0
T3	427030	15	0	0
T4	307288	22	0	0
T11	0	19	0	0
T12	0	79	0	0
T19	657	3	0	0
T20	4193	0	0	0
T21	2231	0	0	0
T22	1661	0	0	0
T23	2574	0	0	0
T34	0	7	0	0
T36	2838	1	0	0
T67	0	1	0	0
T68	0	10	0	0
T69	0	3	0	0
T125	16163	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	258454443	3753	0	0
T2	120596	0	0	0
T3	427030	15	0	0
T4	307288	22	0	0
T11	0	19	0	0
T12	0	79	0	0
T19	657	3	0	0
T20	4193	0	0	0
T21	2231	0	0	0
T22	1661	0	0	0
T23	2574	0	0	0
T34	0	7	0	0
T36	2838	1	0	0
T67	0	1	0	0
T68	0	10	0	0
T69	0	3	0	0
T125	16163	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T4,T3
0	1	Covered	T4,T3,T11
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T36
1	0	Covered	T19,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	518079720	3796	0	0
GateOpen_A	518079720	3796	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518079720	3796	0	0
T2	241244	0	0	0
T3	853926	14	0	0
T4	613657	24	0	0
T11	0	20	0	0
T12	0	76	0	0
T19	1420	3	0	0
T20	4579	0	0	0
T21	4486	0	0	0
T22	2892	0	0	0
T23	5227	0	0	0
T34	0	7	0	0
T36	5755	1	0	0
T67	0	2	0	0
T68	0	9	0	0
T69	0	4	0	0
T125	29452	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	518079720	3796	0	0
T2	241244	0	0	0
T3	853926	14	0	0
T4	613657	24	0	0
T11	0	20	0	0
T12	0	76	0	0
T19	1420	3	0	0
T20	4579	0	0	0
T21	4486	0	0	0
T22	2892	0	0	0
T23	5227	0	0	0
T34	0	7	0	0
T36	5755	1	0	0
T67	0	2	0	0
T68	0	9	0	0
T69	0	4	0	0
T125	29452	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T4,T3
0	1	Covered	T4,T3,T11
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T3,T36
1	0	Covered	T19,T34,T35
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	264579308	3772	0	0
GateOpen_A	264579308	3772	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264579308	3772	0	0
T2	120628	0	0	0
T3	470184	13	0	0
T4	387485	17	0	0
T11	0	20	0	0
T12	0	70	0	0
T19	694	1	0	0
T20	2290	0	0	0
T21	2243	0	0	0
T22	1446	0	0	0
T23	2614	0	0	0
T34	0	6	0	0
T36	2878	1	0	0
T67	0	1	0	0
T68	0	11	0	0
T69	0	3	0	0
T125	14727	0	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	264579308	3772	0	0
T2	120628	0	0	0
T3	470184	13	0	0
T4	387485	17	0	0
T11	0	20	0	0
T12	0	70	0	0
T19	694	1	0	0
T20	2290	0	0	0
T21	2243	0	0	0
T22	1446	0	0	0
T23	2614	0	0	0
T34	0	6	0	0
T36	2878	1	0	0
T67	0	1	0	0
T68	0	11	0	0
T69	0	3	0	0
T125	14727	0	0	0