Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326488608

1

T4

1922

T1

361084

T5

2854

auto[1]

428108

1

T17

576

T18

344

T19

654

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326502542

1

T4

1922

T1

361084

T5

2854

auto[1]

414174

1

T17

346

T18

116

T19

504

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

326412622

1

T4

1922

T1

361084

T5

2854

auto[1]

504094

1

T17

760

T18

340

T19

582

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

308279742

1

T4

1922

T1

361084

T5

2854

auto[1]

18636974

1

T17

818

T18

4072

T19

3462

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

194025492

1

T4

250

T1

361084

T5

2854

auto[1]

132891224

1

T4

1672

T15

1450

T2

18

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

177908800

1

T4

250

T1

361084

T5

2854

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130020462

1

T4

1672

T15

1450

T2

18

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30638

1

T17

36

T19

22

T76

34

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7390

1

T17

12

T137

20

T7

40

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

15509224

1

T17

300

T18

3688

T19

368

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2747124

1

T17

162

T19

2458

T76

72

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54522

1

T17

16

T18

52

T19

50

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13754

1

T17

26

T19

88

T76

26

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

64770

1

T17

42

T19

30

T26

1122

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1510

1

T76

30

T84

8

T192

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

12946

1

T136

102

T87

40

T168

60

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3162

1

T192

58

T169

68

T193

52

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10972

1

T18

8

T76

18

T136

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2728

1

T19

20

T135

44

T7

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

19196

1

T18

44

T76

94

T136

108

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5424

1

T19

124

T135

56

T7

122

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

55610

1

T17

146

T18

24

T19

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

4352

1

T135

12

T7

20

T83

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31838

1

T17

120

T18

36

T76

94

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8524

1

T7

78

T192

58

T12

60

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30040

1

T17

16

T18

58

T19

48

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6482

1

T17

8

T7

34

T161

14

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

60478

1

T17

106

T18

158

T19

184

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13304

1

T17

60

T7

142

T161

114

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

61668

1

T17

16

T19

82

T135

38

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6654

1

T17

26

T137

8

T7

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47018

1

T17

38

T19

126

T137

48

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14400

1

T17

100

T137

90

T7

136

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

45234

1

T17

32

T18

10

T19

40

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12978

1

T17

30

T19

22

T76

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

82538

1

T17

62

T18

54

T19

60

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

22976

1

T76

70

T136

50

T7

44