---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_io_div2_meas.u_meas.MaxWidth_A	0	0	255607360	0	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21691736	0	0	0
tb.dut.u_io_div4_meas.u_meas.MaxWidth_A	0	0	127803126	0	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21691736	0	0	0
tb.dut.u_io_meas.u_meas.MaxWidth_A	0	0	512817371	0	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21691736	0	0	0
tb.dut.u_main_meas.u_meas.MaxWidth_A	0	0	544924323	0	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21691736	0	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	256899523	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	128449202	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	515497665	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	547716408	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	262770787	0	0	1010
tb.dut.u_usb_meas.u_meas.MaxWidth_A	0	0	261430617	0	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckHoldReq	0	0	21691736	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	165013878	162682541	0	0
tb.dut.AllClkBypReqKnownO_A	0	0	165013878	162682541	0	0
tb.dut.CgEnKnownO_A	0	0	165013878	162682541	0	0
tb.dut.ClocksKownO_A	0	0	165013878	162682541	0	0
tb.dut.FpvSecCmClkMainAesCountCheck_A	0	0	165013878	11	0	0
tb.dut.FpvSecCmClkMainHmacCountCheck_A	0	0	165013878	12	0	0
tb.dut.FpvSecCmClkMainKmacCountCheck_A	0	0	165013878	12	0	0
tb.dut.FpvSecCmClkMainOtbnCountCheck_A	0	0	165013878	9	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	165013878	90	0	0
tb.dut.IoClkBypReqKnownO_A	0	0	165013878	162682541	0	0
tb.dut.JitterEnableKnownO_A	0	0	165013878	162682541	0	0
tb.dut.LcCtrlClkBypAckKnownO_A	0	0	165013878	162682541	0	0
tb.dut.PwrMgrKnownO_A	0	0	165013878	162682541	0	0
tb.dut.TlAReadyKnownO_A	0	0	165013878	162682541	0	0
tb.dut.TlDValidKnownO_A	0	0	165013878	162682541	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStart_A	0	0	544924763	4116	0	0
tb.dut.clkmgr_aes_trans_sva_if.TransStop_A	0	0	544924763	2118	0	0
tb.dut.clkmgr_aon_cg_aon_peri.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_secure.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_aon_timers.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div2_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_div4_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_io_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_main_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_aon_cg_usb_powerup.CgEn_A	0	0	805	805	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOff_A	0	0	255607360	158	0	0
tb.dut.clkmgr_cg_io_div2_infra.CgEnOn_A	0	0	255607360	158	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOff_A	0	0	255607360	7977	0	0
tb.dut.clkmgr_cg_io_div2_peri.CgEnOn_A	0	0	255607360	5593	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOff_A	0	0	127803126	158	0	0
tb.dut.clkmgr_cg_io_div4_infra.CgEnOn_A	0	0	127803126	158	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOff_A	0	0	127803126	7954	0	0
tb.dut.clkmgr_cg_io_div4_peri.CgEnOn_A	0	0	127803126	5570	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOff_A	0	0	127803126	158	0	0
tb.dut.clkmgr_cg_io_div4_secure.CgEnOn_A	0	0	127803126	158	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOff_A	0	0	127803126	158	0	0
tb.dut.clkmgr_cg_io_div4_timers.CgEnOn_A	0	0	127803126	158	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOff_A	0	0	512817371	158	0	0
tb.dut.clkmgr_cg_io_infra.CgEnOn_A	0	0	512817371	147	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOff_A	0	0	512817371	7985	0	0
tb.dut.clkmgr_cg_io_peri.CgEnOn_A	0	0	512817371	5590	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOff_A	0	0	544924323	4258	0	0
tb.dut.clkmgr_cg_main_aes.CgEnOn_A	0	0	544924323	4257	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOff_A	0	0	544924323	4266	0	0
tb.dut.clkmgr_cg_main_hmac.CgEnOn_A	0	0	544924323	4265	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOff_A	0	0	544924323	142	0	0
tb.dut.clkmgr_cg_main_infra.CgEnOn_A	0	0	544924323	141	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOff_A	0	0	544924323	4261	0	0
tb.dut.clkmgr_cg_main_kmac.CgEnOn_A	0	0	544924323	4260	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOff_A	0	0	544924323	4279	0	0
tb.dut.clkmgr_cg_main_otbn.CgEnOn_A	0	0	544924323	4278	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOff_A	0	0	544924323	142	0	0
tb.dut.clkmgr_cg_main_secure.CgEnOn_A	0	0	544924323	141	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOff_A	0	0	261430617	7970	0	0
tb.dut.clkmgr_cg_usb_peri.CgEnOn_A	0	0	261430617	5573	0	0
tb.dut.clkmgr_csr_assert.TlulOOBAddrErr_A	0	0	165894211	5140799	0	0
tb.dut.clkmgr_csr_assert.clk_enables_rd_A	0	0	165894211	59218	0	0
tb.dut.clkmgr_csr_assert.clk_hints_rd_A	0	0	165894211	52819	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_rd_A	0	0	165894211	65255	0	0
tb.dut.clkmgr_csr_assert.extclk_ctrl_regwen_rd_A	0	0	165894211	50322	0	0
tb.dut.clkmgr_csr_assert.jitter_enable_rd_A	0	0	165894211	73450	0	0
tb.dut.clkmgr_csr_assert.jitter_regwen_rd_A	0	0	165894211	57348	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Stepped_A	0	0	512817797	4381	0	0
tb.dut.clkmgr_div2_sva_if.g_div2.Div2Whole_A	0	0	512817797	5225	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Stepped_A	0	0	255607763	4288	0	0
tb.dut.clkmgr_div4_sva_if.g_div4.Div4Whole_A	0	0	255607763	5002	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqFall_A	0	0	165013878	4194	0	0
tb.dut.clkmgr_extclk_sva_if.AllClkBypReqRise_A	0	0	165013878	4194	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelFall_A	0	0	165013878	2493	0	0
tb.dut.clkmgr_extclk_sva_if.HiSpeedSelRise_A	0	0	165013878	2493	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqFall_A	0	0	165013878	5214	0	0
tb.dut.clkmgr_extclk_sva_if.IoClkBypReqRise_A	0	0	165013878	5213	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStart_A	0	0	544924763	4124	0	0
tb.dut.clkmgr_hmac_trans_sva_if.TransStop_A	0	0	544924763	2124	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateClose_A	0	0	255607763	3605	0	0
tb.dut.clkmgr_io_div2_peri_sva_if.GateOpen_A	0	0	255607763	3605	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateClose_A	0	0	127803513	3604	0	0
tb.dut.clkmgr_io_div4_peri_sva_if.GateOpen_A	0	0	127803513	3604	0	0
tb.dut.clkmgr_io_peri_sva_if.GateClose_A	0	0	512817797	3593	0	0
tb.dut.clkmgr_io_peri_sva_if.GateOpen_A	0	0	512817797	3593	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStart_A	0	0	544924763	4119	0	0
tb.dut.clkmgr_kmac_trans_sva_if.TransStop_A	0	0	544924763	2135	0	0
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if.CtrlEnOn_A	0	0	165013878	12090	0	0
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if.CtrlEnOn_A	0	0	165013878	16508	0	0
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if.CtrlEnOn_A	0	0	165013878	25458	0	0
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if.CtrlEnOn_A	0	0	165013878	11826	0	0
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	165013878	19339301	0	55
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if.CtrlEnOn_A	0	0	165013878	16612	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStart_A	0	0	544924763	4137	0	0
tb.dut.clkmgr_otbn_trans_sva_if.TransStop_A	0	0	544924763	2116	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusFall_A	0	0	165013878	145	0	0
tb.dut.clkmgr_pwrmgr_sva_if.IoStatusRise_A	0	0	165013878	145	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusFall_A	0	0	165013878	140	0	0
tb.dut.clkmgr_pwrmgr_sva_if.MainStatusRise_A	0	0	165013878	140	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusFall_A	0	0	165013878	150	0	0
tb.dut.clkmgr_pwrmgr_sva_if.UsbStatusRise_A	0	0	165013878	150	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqFalse_A	0	0	165013878	162543129	0	0
tb.dut.clkmgr_sec_cm_checker_assert.AllClkBypReqTrue_A	0	0	165013878	137015	0	0
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	165013878	162461296	0	2415
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqTrue_A	0	0	165013878	214054	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckFalse_A	0	0	165013878	162555986	0	0
tb.dut.clkmgr_sec_cm_checker_assert.LcClkBypAckTrue_A	0	0	165013878	124158	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateClose_A	0	0	261431011	3610	0	0
tb.dut.clkmgr_usb_peri_sva_if.GateOpen_A	0	0	261431011	3610	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	165894211	20960079	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	165894211	163458358	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	165894211	163458358	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	165894211	23773401	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	165894211	163458358	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	165894211	163458358	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
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tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	1010	1010	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	165894831	17267949	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	165894211	2769834	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	165894831	210653	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	165894831	135185	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	165894211	3063190	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	165894831	20960079	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	165894831	23773401	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	165894831	20960079	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	165894831	23773401	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	165894831	23773401	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	165894831	23773401	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	165894211	1654337	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	165894211	1258832	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	1010	1010	0	0
tb.dut.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_calib_rdy_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clk_io_div2_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_io_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_io_peri_scanmode_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_io_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	544924323	33613	0	0
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	544924323	34031	0	0
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	544924323	33645	0	0
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	544924323	33732	0	0
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	544924323	540276186	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clk_usb_peri_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	165013878	19637	0	0
tb.dut.u_clkmgr_byp.u_all_byp_req.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_en_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_en_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clkmgr_byp.u_hi_speed_sel.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	165013878	17152	0	0
tb.dut.u_clkmgr_byp.u_io_byp_req.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_div2_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_div_scanmode_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_io_div2_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	165013878	162682541	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	165013878	2974	0	0
tb.dut.u_io_div2_meas.u_err_sync.SyncReqAckHoldReq	0	0	255607360	2974	0	0
tb.dut.u_io_div2_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	255607360	4808718	0	0
tb.dut.u_io_div2_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	255607360	91002	0	0
tb.dut.u_io_div2_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21206739	89974	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	255607360	255607360	0	0
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	255607360	255607360	0	0
tb.dut.u_io_div4_div_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_div_scanmode_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_io_div4_div_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	165013878	162682541	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	165013878	2786	0	0
tb.dut.u_io_div4_meas.u_err_sync.SyncReqAckHoldReq	0	0	127803126	2785	0	0
tb.dut.u_io_div4_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	127803126	4581326	0	0
tb.dut.u_io_div4_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	127803126	90095	0	0
tb.dut.u_io_div4_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21206739	89073	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	127803126	127803126	0	0
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	127803126	127803126	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	165013878	3178	0	0
tb.dut.u_io_meas.u_err_sync.SyncReqAckHoldReq	0	0	512817371	3178	0	0
tb.dut.u_io_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	512817371	4808848	0	0
tb.dut.u_io_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	512817371	91615	0	0
tb.dut.u_io_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21206739	90586	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	512817371	510633693	0	0
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	512817371	510633693	0	0
tb.dut.u_io_step_down_req_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_io_step_down_req_sync.OutputsKnown_A	0	0	512817371	508442735	0	0
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	512817371	508435544	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputIfUnstable_A	0	0	512817371	27526	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_main_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	165013878	2897	0	0
tb.dut.u_main_meas.u_err_sync.SyncReqAckHoldReq	0	0	544924323	2897	0	0
tb.dut.u_main_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	544924323	4812936	0	0
tb.dut.u_main_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	544924323	110244	0	0
tb.dut.u_main_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21638997	109882	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	544924323	542611103	0	0
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	544924323	542611103	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown0	0	0	255317428	255316623	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic.selKnown1	0	0	512817371	512816566	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	255607360	255606555	0	0
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	512817371	512816566	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.DivEven_A	0	0	805	805	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown0	0	0	127803126	127802321	0	0
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic.selKnown1	0	0	512817371	512816566	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra.OutputsKnown_A	0	0	255607360	254511413	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri.OutputsKnown_A	0	0	255607360	254511413	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra.OutputsKnown_A	0	0	127803126	127255218	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri.OutputsKnown_A	0	0	127803126	127255218	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure.OutputsKnown_A	0	0	127803126	127255218	0	0
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers.OutputsKnown_A	0	0	127803126	127255218	0	0
tb.dut.u_prim_mubi4_sender_clk_io_infra.OutputsKnown_A	0	0	512817371	508442735	0	0
tb.dut.u_prim_mubi4_sender_clk_io_peri.OutputsKnown_A	0	0	512817371	508442735	0	0
tb.dut.u_prim_mubi4_sender_clk_main_infra.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_prim_mubi4_sender_clk_main_secure.OutputsKnown_A	0	0	544924323	540276186	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_infra.OutputsKnown_A	0	0	261430617	259200576	0	0
tb.dut.u_prim_mubi4_sender_clk_usb_peri.OutputsKnown_A	0	0	261430617	259200576	0	0
tb.dut.u_reg.en2addrHit	0	0	165894211	821288	0	0
tb.dut.u_reg.reAfterRv	0	0	165894211	821288	0	0
tb.dut.u_reg.rePulse	0	0	165894211	196222	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	165894211	135181	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.DstReqKnown_A	0	0	256899523	255753961	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	165894211	24555	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	256899523	1175	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	165894211	25730	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	256899523	24555	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	256899523	24555	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	24555	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	165894211	163840	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	256899523	255753961	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	165894211	30377	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	165894211	30374	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	256899523	30389	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	256899523	30384	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	30405	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	256899523	255753961	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	165894211	25	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	256899523	25	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	256899523	255753961	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	165894211	25	0	0
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	256899523	25	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	165894211	218454	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.DstReqKnown_A	0	0	128449202	127876547	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	165894211	24555	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	128449202	1175	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	165894211	25730	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	128449202	24550	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	128449202	24555	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	24555	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	165894211	266160	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	128449202	127876547	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	165894211	30519	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	165894211	30518	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	128449202	30527	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	128449202	30524	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	30555	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	128449202	127876547	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	165894211	33	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	128449202	33	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	128449202	127876547	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	165894211	30	0	0
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	128449202	30	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	165894211	93911	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.DstReqKnown_A	0	0	515497665	510927899	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	165894211	24555	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	515497665	1175	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	165894211	25730	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	515497665	24555	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	515497665	24555	0	0
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	24555	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	165894211	114648	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	515497665	510927899	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	165894211	30529	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	165894211	30527	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	515497665	30536	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	515497665	30534	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	30548	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	515497665	510927899	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	165894211	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	515497665	36	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	515497665	510927899	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	165894211	35	0	0
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	515497665	35	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	165894211	91883	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.DstReqKnown_A	0	0	547716408	542865010	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	165894211	24555	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	547716408	1175	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	165894211	25730	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	547716408	24555	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	547716408	24555	0	0
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	24555	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	165894211	112401	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	547716408	542865010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	165894211	30508	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	165894211	30505	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	547716408	30517	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	547716408	30514	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	30525	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	547716408	542865010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	165894211	46	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	547716408	46	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	547716408	542865010	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	165894211	45	0	0
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	547716408	45	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.BusySrcReqChk_A	0	0	165894211	132946	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.DstReqKnown_A	0	0	262770787	260443216	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcAckBusyChk_A	0	0	165894211	24050	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	262770787	1175	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	165894211	25225	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	262770787	24015	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	262770787	24069	0	0
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	24555	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.BusySrcReqChk_A	0	0	165894211	164299	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.DstReqKnown_A	0	0	262770787	260443216	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcAckBusyChk_A	0	0	165894211	30322	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.SrcBusyKnown_A	0	0	165894211	163458358	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	165894211	30288	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	262770787	30544	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	262770787	30490	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	165894211	30617	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi.MubiIsNotYetSupported_A	0	0	262770787	260443216	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.DstPulseCheck_A	0	0	165894211	46	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync.SrcPulseCheck_M	0	0	262770787	46	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.CheckSwAccessIsLegal_A	0	0	1010	1010	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo.MubiIsNotYetSupported_A	0	0	262770787	260443216	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.DstPulseCheck_A	0	0	165894211	42	0	0
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync.SrcPulseCheck_M	0	0	262770787	42	0	0
tb.dut.u_reg.wePulse	0	0	165894211	625066	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.OutputsKnown_A	0	0	165013878	162682541	0	0
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_usb_meas.u_err_sync.SyncReqAckAckNeedsReq	0	0	165013878	2623	0	0
tb.dut.u_usb_meas.u_err_sync.SyncReqAckHoldReq	0	0	261430617	2623	0	0
tb.dut.u_usb_meas.u_meas.RefCntVal_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout.SyncReqAckAckNeedsReq	0	0	261430617	4812786	0	0
tb.dut.u_usb_meas.u_meas.gen_timeout_assert.ClkRatios_A	0	0	805	805	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.DstPulseCheck_A	0	0	261430617	108405	0	0
tb.dut.u_usb_meas.u_meas.u_sync_ref.SrcPulseCheck_M	0	0	21675965	107537	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	805	805	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.OutputsKnown_A	0	0	261430617	260317994	0	0
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	261430617	260317994	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.clkmgr_lost_calib_regwen_sva_if.RegwenOff_A	0	0	165013878	19339301	0	55
tb.dut.clkmgr_sec_cm_checker_assert.IoClkBypReqFalse_A	0	0	165013878	162461296	0	2415
tb.dut.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	544924323	540268954	0	2415
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clkmgr_byp.u_en_sync.gen_flops.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_flops.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.OutputDelay_A	0	0	512817371	508435544	0	2415
tb.dut.u_main_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	256899523	0	0	1010
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	128449202	0	0	1010
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	515497665	0	0	1010
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	547716408	0	0	1010
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	262770787	0	0	1010
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_flops.gen_no_stable_chks.OutputDelay_A	0	0	165013878	162675174	0	2415

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	165894831	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	165894831	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	165894831	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	165894831	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	165894831	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	165894831	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	165894831	9083	9083	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	165894831	2459	2459	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	165894831	12014	12014	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	165894831	95434	95434	755

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	165894831	9083	9083	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	165894831	2459	2459	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	165894831	12014	12014	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	165894831	95434	95434	755