3df77bec1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | csrng_smoke | 5.000s | 19.977us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | csrng_csr_hw_reset | 4.000s | 58.177us | 5 | 5 | 100.00 |
| V1 | csr_rw | csrng_csr_rw | 5.000s | 75.231us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | csrng_csr_bit_bash | 30.000s | 2.020ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | csrng_csr_aliasing | 6.000s | 106.137us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 7.000s | 265.435us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 5.000s | 75.231us | 20 | 20 | 100.00 |
| csrng_csr_aliasing | 6.000s | 106.137us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | interrupts | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| V2 | alerts | csrng_alert | 10.000s | 632.223us | 500 | 500 | 100.00 |
| V2 | err | csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 |
| V2 | cmds | csrng_cmds | 1.100m | 3.060ms | 50 | 50 | 100.00 |
| V2 | life cycle | csrng_cmds | 1.100m | 3.060ms | 50 | 50 | 100.00 |
| V2 | stress_all | csrng_stress_all | 2.350m | 11.268ms | 50 | 50 | 100.00 |
| V2 | intr_test | csrng_intr_test | 5.000s | 18.123us | 50 | 50 | 100.00 |
| V2 | alert_test | csrng_alert_test | 8.000s | 91.779us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | csrng_tl_errors | 13.000s | 362.738us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | csrng_tl_errors | 13.000s | 362.738us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 4.000s | 58.177us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 75.231us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 106.137us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 42.812us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | csrng_csr_hw_reset | 4.000s | 58.177us | 5 | 5 | 100.00 |
| csrng_csr_rw | 5.000s | 75.231us | 20 | 20 | 100.00 | ||
| csrng_csr_aliasing | 6.000s | 106.137us | 5 | 5 | 100.00 | ||
| csrng_same_csr_outstanding | 5.000s | 42.812us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1428 | 1440 | 99.17 | |||
| V2S | tl_intg_err | csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 |
| csrng_tl_intg_err | 10.000s | 444.278us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | csrng_regwen | 5.000s | 54.658us | 50 | 50 | 100.00 |
| csrng_csr_rw | 5.000s | 75.231us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_mubi | csrng_alert | 10.000s | 632.223us | 500 | 500 | 100.00 |
| V2S | sec_cm_intersig_mubi | csrng_stress_all | 2.350m | 11.268ms | 50 | 50 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_update_fsm_sparse | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_ctrl_mubi | csrng_alert | 10.000s | 632.223us | 500 | 500 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| V2S | sec_cm_constants_lc_gated | csrng_stress_all | 2.350m | 11.268ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 10.000s | 632.223us | 500 | 500 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 10.000s | 444.278us | 20 | 20 | 100.00 |
| V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| csrng_sec_cm | 16.000s | 324.454us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 7.000s | 348.083us | 200 | 200 | 100.00 |
| csrng_err | 5.000s | 20.310us | 488 | 500 | 97.60 | ||
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 49.283m | 45.707ms | 6 | 50 | 12.00 |
| V3 | TOTAL | 6 | 50 | 12.00 | |||
| TOTAL | 1614 | 1670 | 96.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 9 | 9 | 8 | 88.89 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 92.84 | 93.34 | 84.27 | 95.41 | 86.47 | 92.23 | 100.00 | 97.33 | 95.87 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 25 failures:
0.csrng_stress_all_with_rand_reset.424821984
Line 246, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10002253359 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0xa6ebc294) == 0x6
UVM_INFO @ 10002253359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.csrng_stress_all_with_rand_reset.3923665477
Line 687, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 31058883478 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x483b9c14) == 0x6
UVM_INFO @ 31058883478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == * has 12 failures:
3.csrng_stress_all_with_rand_reset.1960992318
Line 301, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25787853202 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x44792994) == 0x6
UVM_INFO @ 25787853202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.csrng_stress_all_with_rand_reset.1901947110
Line 270, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/8.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10001703544 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x90a9c514) == 0x6
UVM_INFO @ 10001703544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:
26.csrng_err.1968758448
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3941112 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 3941112 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3941112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
92.csrng_err.105401850
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/92.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 3715029 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 3715029 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 3715029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 4 failures:
80.csrng_err.2589258224
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/80.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 6768529 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 6768529 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 6768529 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 6768529 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 6768529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
119.csrng_err.2987166123
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/119.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1853826 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1853826 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1853826 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1853826 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1853826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 3 failures:
19.csrng_stress_all_with_rand_reset.695486560
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 11427099 PS + 12
Verilog Stack Trace:
27.csrng_stress_all_with_rand_reset.2544810021
Line 281, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/27.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 5002811246 PS + 12
Verilog Stack Trace:
... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:
1.csrng_stress_all_with_rand_reset.1765017739
Line 468, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 20573183664 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 20573183664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.csrng_stress_all_with_rand_reset.3773933941
Line 583, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 40638547414 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
UVM_INFO @ 40638547414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: * has 2 failures:
7.csrng_stress_all_with_rand_reset.3898977520
Line 351, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13419954473 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 13419954473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.csrng_stress_all_with_rand_reset.289133273
Line 384, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 15974287246 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 15974287246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:
131.csrng_err.2666045894
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/131.csrng_err/latest/run.log
workdir : /workspace/coverage
dutinst : tb.dut(csrng)
scope : default
testname : 131.csrng_err.2666045894
coverage files:
model(design data) : /workspace/coverage/default/131.csrng_err.2666045894/icc_2fd05324_376d948a.ucm
data : /workspace/coverage/default/131.csrng_err.2666045894/icc_2fd05324_376d948a.ucd
TOOL: xrun(64) 21.09-s006: Exiting on May 17, 2023 at 01:04:50 PDT (total: 00:00:04)
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:144: simulate] Error 1
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
430.csrng_err.3377469276
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/430.csrng_err/latest/run.log
UVM_ERROR @ 15123709 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
UVM_INFO @ 15123709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---