CSRNG Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: `9f20940d49`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	20.000s	171.149us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	148.179us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	82.424us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	46.000s	2.509ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	134.197us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	127.282us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	82.424us	20	20	100.00
		csrng_csr_aliasing	10.000s	134.197us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	23.000s	46.929us	199	200	99.50
V2	alerts	csrng_alert	2.033m	8.275ms	500	500	100.00
V2	err	csrng_err	25.000s	19.029us	499	500	99.80
V2	cmds	csrng_cmds	9.667m	46.931ms	50	50	100.00
V2	life cycle	csrng_cmds	9.667m	46.931ms	50	50	100.00
V2	stress_all	csrng_stress_all	45.350m	172.389ms	49	50	98.00
V2	intr_test	csrng_intr_test	5.000s	159.113us	50	50	100.00
V2	alert_test	csrng_alert_test	18.000s	14.149us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	26.000s	1.240ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	26.000s	1.240ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	148.179us	5	5	100.00
		csrng_csr_rw	5.000s	82.424us	20	20	100.00
		csrng_csr_aliasing	10.000s	134.197us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	325.993us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	148.179us	5	5	100.00
		csrng_csr_rw	5.000s	82.424us	20	20	100.00
		csrng_csr_aliasing	10.000s	134.197us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	325.993us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	20.000s	35.843us	5	5	100.00
		csrng_tl_intg_err	34.000s	610.854us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	19.000s	50.407us	50	50	100.00
		csrng_csr_rw	5.000s	82.424us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.033m	8.275ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	45.350m	172.389ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.033m	8.275ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	45.350m	172.389ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.033m	8.275ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	34.000s	610.854us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
		csrng_sec_cm	20.000s	35.843us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	23.000s	46.929us	199	200	99.50
		csrng_err	25.000s	19.029us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	31.217m	48.957ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.35	98.37	96.16	99.09	96.70	91.90	100.00	97.32	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.14829217578719795633610252176564381722553085240899927092234480021013821367750
    Line 98, in log /workspaces/repo/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 832472180 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 832472180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.63605592953915080349557019341416230702727540278624749591753661039364323858821
    Line 97, in log /workspaces/repo/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1574924086 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1574924086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 38.csrng_stress_all.2522804043499442756826027096066320403508180745948242341276016938544437263665
    Line 158, in log /workspaces/repo/scratch/os_regression/csrng-sim-xcelium/38.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 7198708269 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 7198708269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

75.csrng_intr.73553050815043228801655715941003078008048396988126206254527864542815522181186
Line 127, in log /workspaces/repo/scratch/os_regression/csrng-sim-xcelium/75.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 110444777 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 110444777 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 110444777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 139.csrng_err.14992941428360891687687457761217171085241342900512453583148013449071601292878
    Line 127, in log /workspaces/repo/scratch/os_regression/csrng-sim-xcelium/139.csrng_err/latest/run.log
```
  UVM_ERROR @  12182177 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  12182177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```