CSRNG Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: a47820eb4c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 6.000s 271.759us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 4.000s 144.500us 5 5 100.00
V1 csr_rw csrng_csr_rw 5.000s 35.997us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 40.000s 1.729ms 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 7.000s 137.720us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 7.000s 387.681us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 5.000s 35.997us 20 20 100.00
csrng_csr_aliasing 7.000s 137.720us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 6.000s 298.566us 196 200 98.00
V2 alerts csrng_alert 1.167m 4.469ms 500 500 100.00
V2 err csrng_err 13.000s 20.515us 499 500 99.80
V2 cmds csrng_cmds 9.600m 50.865ms 50 50 100.00
V2 life cycle csrng_cmds 9.600m 50.865ms 50 50 100.00
V2 stress_all csrng_stress_all 25.600m 71.535ms 46 50 92.00
V2 intr_test csrng_intr_test 8.000s 32.308us 50 50 100.00
V2 alert_test csrng_alert_test 5.000s 79.653us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 10.000s 162.769us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 10.000s 162.769us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 4.000s 144.500us 5 5 100.00
csrng_csr_rw 5.000s 35.997us 20 20 100.00
csrng_csr_aliasing 7.000s 137.720us 5 5 100.00
csrng_same_csr_outstanding 9.000s 443.752us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 4.000s 144.500us 5 5 100.00
csrng_csr_rw 5.000s 35.997us 20 20 100.00
csrng_csr_aliasing 7.000s 137.720us 5 5 100.00
csrng_same_csr_outstanding 9.000s 443.752us 20 20 100.00
V2 TOTAL 1431 1440 99.38
V2S tl_intg_err csrng_sec_cm 7.000s 308.904us 5 5 100.00
csrng_tl_intg_err 18.000s 326.874us 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 4.000s 101.906us 50 50 100.00
csrng_csr_rw 5.000s 35.997us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 1.167m 4.469ms 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 25.600m 71.535ms 46 50 92.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 1.167m 4.469ms 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
V2S sec_cm_constants_lc_gated csrng_stress_all 25.600m 71.535ms 46 50 92.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 1.167m 4.469ms 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 18.000s 326.874us 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
csrng_sec_cm 7.000s 308.904us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 6.000s 298.566us 196 200 98.00
csrng_err 13.000s 20.515us 499 500 99.80
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 24.617m 83.727ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1611 1630 98.83

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 6 66.67
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.19 98.26 95.90 98.89 96.59 91.90 100.00 97.32 90.63

Failure Buckets

Past Results