CSRNG Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	14.896us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	13.255us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	20.695us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	337.790us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	156.174us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	33.773us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	20.695us	20	20	100.00
		csrng_csr_aliasing	7.000s	156.174us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	85.870us	200	200	100.00
V2	alerts	csrng_alert	19.000s	46.065us	500	500	100.00
V2	err	csrng_err	16.000s	46.042us	474	500	94.80
V2	cmds	csrng_cmds	6.417m	29.335ms	41	50	82.00
V2	life cycle	csrng_cmds	6.417m	29.335ms	41	50	82.00
V2	stress_all	csrng_stress_all	20.983m	108.962ms	49	50	98.00
V2	intr_test	csrng_intr_test	13.000s	42.144us	50	50	100.00
V2	alert_test	csrng_alert_test	15.000s	14.140us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	117.532us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	117.532us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	13.255us	5	5	100.00
		csrng_csr_rw	8.000s	20.695us	20	20	100.00
		csrng_csr_aliasing	7.000s	156.174us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	31.152us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	13.255us	5	5	100.00
		csrng_csr_rw	8.000s	20.695us	20	20	100.00
		csrng_csr_aliasing	7.000s	156.174us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	31.152us	20	20	100.00
V2		TOTAL			1404	1440	97.50
V2S	tl_intg_err	csrng_sec_cm	9.000s	135.506us	5	5	100.00
		csrng_tl_intg_err	11.000s	102.331us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	62.548us	50	50	100.00
		csrng_csr_rw	8.000s	20.695us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	19.000s	46.065us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.983m	108.962ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	19.000s	46.065us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.983m	108.962ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	19.000s	46.065us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	102.331us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
		csrng_sec_cm	9.000s	135.506us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	85.870us	200	200	100.00
		csrng_err	16.000s	46.042us	474	500	94.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.841h	518.819ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			1584	1670	94.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.60	93.12	84.08	95.33	85.99	91.67	100.00	97.50	94.96

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test csrng_stress_all_with_rand_reset has 29 failures.
  - 0.csrng_stress_all_with_rand_reset.5489493658164998396492390456203889435866683675152800115256357484210098011343
    Line 304, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14548929931 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14548929931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.55422178244387910433993296583184366755039670288765029168329837508630891164854
    Line 329, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13362581596 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13362581596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test csrng_stress_all_with_rand_reset has 21 failures.
  - 1.csrng_stress_all_with_rand_reset.38296075377619152762374863704633172578041274608527131512008169275222336806485
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2600077958 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2600077958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.csrng_stress_all_with_rand_reset.95374549435602254096214187276039429888528735091339792775228257501134504325001
    Line 288, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5803440008 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5803440008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 19 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 15 failures:

Test csrng_cmds has 9 failures.

14.csrng_cmds.95182035004651728526734056259565018301446717404710708095965116618247735227342
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  14.csrng_cmds.4226429902
  
  coverage files:
    model(design data) :  /workspace/coverage/default/14.csrng_cmds.4226429902/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/14.csrng_cmds.4226429902/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 21, 2024 at 12:35:29 PDT  (total: 00:00:52)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

22.csrng_cmds.54470462115185447526220006884056259585527220020127996572781661776936489115815
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/22.csrng_cmds/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  22.csrng_cmds.2844713127
  
  coverage files:
    model(design data) :  /workspace/coverage/default/22.csrng_cmds.2844713127/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/22.csrng_cmds.2844713127/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 21, 2024 at 12:36:19 PDT  (total: 00:01:41)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 7 more failures.

Test csrng_err has 6 failures.

31.csrng_err.35766813475331860618896396221786982313596950185507086942676393577533731751188
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/31.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  31.csrng_err.2222441748
  
  coverage files:
    model(design data) :  /workspace/coverage/default/31.csrng_err.2222441748/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/31.csrng_err.2222441748/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 21, 2024 at 12:35:06 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

141.csrng_err.110801264394380913582333040549992269060040507455110372738809857084074033827480
Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/141.csrng_err/latest/run.log

    workdir  :  /workspace/coverage
    dutinst  :  tb.dut(csrng)
    scope    :  default
    testname :  141.csrng_err.3350351512
  
  coverage files:
    model(design data) :  /workspace/coverage/default/141.csrng_err.3350351512/icc_69c9a0ec_01c5caa7.ucm
    data               :  /workspace/coverage/default/141.csrng_err.3350351512/icc_69c9a0ec_01c5caa7.ucd
  TOOL:    xrun(64)    21.09-s006: Exiting on Apr 21, 2024 at 12:36:01 PDT  (total: 00:00:03)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 1

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,151): Assertion DataKnown_A has failed has 10 failures:

Test csrng_err has 10 failures.

26.csrng_err.47919051571890405264098198994161416035330446101695171553717771993913821515439
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3029206 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3029206 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3029206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

74.csrng_err.45016389578524659461270566695523531181083199504786886488209179784500304057150
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/74.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,151): (time 3801360 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   3801360 ps: (prim_fifo_sync.sv:151) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   3801360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 9 failures:

Test csrng_err has 9 failures.

132.csrng_err.11268111955086257100007011755427426461910711938567139576740825290515302140994
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/132.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1715022 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1715022 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1715022 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1715022 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1715022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

186.csrng_err.35991440551239644331714981564940191314365338379725107480882180677472408513512
Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/186.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5966812 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5966812 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5966812 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5966812 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5966812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 7 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:161) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 26.csrng_stress_all.30094392272656899350373717145794919186958182429671611347278425060764232309235
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  96636183 ps: (csrng_scoreboard.sv:161) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  96636183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 151.csrng_err.81940950691847857388475130754446128618568967361985895348193491861738142766316
    Line 311, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/151.csrng_err/latest/run.log
```
  UVM_ERROR @   7448444 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   7448444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```