CSRNG Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 5.000s 138.991us 50 50 100.00
V1 csr_hw_reset csrng_csr_hw_reset 3.000s 149.997us 5 5 100.00
V1 csr_rw csrng_csr_rw 5.000s 32.132us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 18.000s 1.390ms 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 5.000s 77.907us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 6.000s 48.686us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 5.000s 32.132us 20 20 100.00
csrng_csr_aliasing 5.000s 77.907us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 interrupts csrng_intr 6.000s 334.990us 200 200 100.00
V2 alerts csrng_alert 8.000s 532.910us 500 500 100.00
V2 err csrng_err 5.000s 21.206us 493 500 98.60
V2 cmds csrng_cmds 2.167m 10.982ms 50 50 100.00
V2 life cycle csrng_cmds 2.167m 10.982ms 50 50 100.00
V2 stress_all csrng_stress_all 1.900m 8.450ms 47 50 94.00
V2 intr_test csrng_intr_test 6.000s 140.944us 50 50 100.00
V2 alert_test csrng_alert_test 5.000s 41.926us 50 50 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 11.000s 145.541us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 11.000s 145.541us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 3.000s 149.997us 5 5 100.00
csrng_csr_rw 5.000s 32.132us 20 20 100.00
csrng_csr_aliasing 5.000s 77.907us 5 5 100.00
csrng_same_csr_outstanding 5.000s 137.939us 20 20 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 3.000s 149.997us 5 5 100.00
csrng_csr_rw 5.000s 32.132us 20 20 100.00
csrng_csr_aliasing 5.000s 77.907us 5 5 100.00
csrng_same_csr_outstanding 5.000s 137.939us 20 20 100.00
V2 TOTAL 1430 1440 99.31
V2S tl_intg_err csrng_sec_cm 7.000s 186.994us 5 5 100.00
csrng_tl_intg_err 15.000s 1.579ms 20 20 100.00
V2S sec_cm_config_regwen csrng_regwen 6.000s 20.790us 50 50 100.00
csrng_csr_rw 5.000s 32.132us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 8.000s 532.910us 500 500 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 1.900m 8.450ms 47 50 94.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_ctrl_mubi csrng_alert 8.000s 532.910us 500 500 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
V2S sec_cm_constants_lc_gated csrng_stress_all 1.900m 8.450ms 47 50 94.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 8.000s 532.910us 500 500 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 15.000s 1.579ms 20 20 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
csrng_sec_cm 7.000s 186.994us 5 5 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 6.000s 334.990us 200 200 100.00
csrng_err 5.000s 21.206us 493 500 98.60
V2S TOTAL 75 75 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 1.424h 55.198ms 6 50 12.00
V3 TOTAL 6 50 12.00
TOTAL 1616 1670 96.77

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 7 77.78
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
92.85 93.35 84.31 95.41 86.43 92.29 100.00 97.50 95.64

Failure Buckets

Past Results