f8b3c19a2
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | csrng_smoke | 5.000s | 138.991us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | csrng_csr_hw_reset | 3.000s | 149.997us | 5 | 5 | 100.00 |
V1 | csr_rw | csrng_csr_rw | 5.000s | 32.132us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | csrng_csr_bit_bash | 18.000s | 1.390ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | csrng_csr_aliasing | 5.000s | 77.907us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | csrng_csr_mem_rw_with_rand_reset | 6.000s | 48.686us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | csrng_csr_rw | 5.000s | 32.132us | 20 | 20 | 100.00 |
csrng_csr_aliasing | 5.000s | 77.907us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | interrupts | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
V2 | alerts | csrng_alert | 8.000s | 532.910us | 500 | 500 | 100.00 |
V2 | err | csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 |
V2 | cmds | csrng_cmds | 2.167m | 10.982ms | 50 | 50 | 100.00 |
V2 | life cycle | csrng_cmds | 2.167m | 10.982ms | 50 | 50 | 100.00 |
V2 | stress_all | csrng_stress_all | 1.900m | 8.450ms | 47 | 50 | 94.00 |
V2 | intr_test | csrng_intr_test | 6.000s | 140.944us | 50 | 50 | 100.00 |
V2 | alert_test | csrng_alert_test | 5.000s | 41.926us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | csrng_tl_errors | 11.000s | 145.541us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | csrng_tl_errors | 11.000s | 145.541us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | csrng_csr_hw_reset | 3.000s | 149.997us | 5 | 5 | 100.00 |
csrng_csr_rw | 5.000s | 32.132us | 20 | 20 | 100.00 | ||
csrng_csr_aliasing | 5.000s | 77.907us | 5 | 5 | 100.00 | ||
csrng_same_csr_outstanding | 5.000s | 137.939us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | csrng_csr_hw_reset | 3.000s | 149.997us | 5 | 5 | 100.00 |
csrng_csr_rw | 5.000s | 32.132us | 20 | 20 | 100.00 | ||
csrng_csr_aliasing | 5.000s | 77.907us | 5 | 5 | 100.00 | ||
csrng_same_csr_outstanding | 5.000s | 137.939us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 1430 | 1440 | 99.31 | |||
V2S | tl_intg_err | csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 |
csrng_tl_intg_err | 15.000s | 1.579ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_regwen | csrng_regwen | 6.000s | 20.790us | 50 | 50 | 100.00 |
csrng_csr_rw | 5.000s | 32.132us | 20 | 20 | 100.00 | ||
V2S | sec_cm_config_mubi | csrng_alert | 8.000s | 532.910us | 500 | 500 | 100.00 |
V2S | sec_cm_intersig_mubi | csrng_stress_all | 1.900m | 8.450ms | 47 | 50 | 94.00 |
V2S | sec_cm_main_sm_fsm_sparse | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_update_fsm_sparse | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_blk_enc_fsm_sparse | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_outblk_fsm_sparse | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_gen_cmd_ctr_redun | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_drbg_upd_ctr_redun | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_drbg_gen_ctr_redun | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_ctrl_mubi | csrng_alert | 8.000s | 532.910us | 500 | 500 | 100.00 |
V2S | sec_cm_main_sm_ctr_local_esc | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
V2S | sec_cm_constants_lc_gated | csrng_stress_all | 1.900m | 8.450ms | 47 | 50 | 94.00 |
V2S | sec_cm_sw_genbits_bus_consistency | csrng_alert | 8.000s | 532.910us | 500 | 500 | 100.00 |
V2S | sec_cm_tile_link_bus_integrity | csrng_tl_intg_err | 15.000s | 1.579ms | 20 | 20 | 100.00 |
V2S | sec_cm_aes_cipher_fsm_sparse | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_aes_cipher_fsm_redun | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
V2S | sec_cm_aes_cipher_ctrl_sparse | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
V2S | sec_cm_aes_cipher_fsm_local_esc | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
V2S | sec_cm_aes_cipher_ctr_redun | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
csrng_sec_cm | 7.000s | 186.994us | 5 | 5 | 100.00 | ||
V2S | sec_cm_aes_cipher_data_reg_local_esc | csrng_intr | 6.000s | 334.990us | 200 | 200 | 100.00 |
csrng_err | 5.000s | 21.206us | 493 | 500 | 98.60 | ||
V2S | TOTAL | 75 | 75 | 100.00 | |||
V3 | stress_all_with_rand_reset | csrng_stress_all_with_rand_reset | 1.424h | 55.198ms | 6 | 50 | 12.00 |
V3 | TOTAL | 6 | 50 | 12.00 | |||
TOTAL | 1616 | 1670 | 96.77 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 9 | 9 | 7 | 77.78 |
V2S | 3 | 3 | 3 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
92.85 | 93.35 | 84.31 | 95.41 | 86.43 | 92.29 | 100.00 | 97.50 | 95.64 |
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == *
has 24 failures:
0.csrng_stress_all_with_rand_reset.4189770898
Line 243, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10003614359 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x1fdeb514) == 0x6
UVM_INFO @ 10003614359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.csrng_stress_all_with_rand_reset.191140595
Line 357, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 19609217612 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x35680014) == 0x6
UVM_INFO @ 19609217612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=*) == *
has 13 failures:
3.csrng_stress_all_with_rand_reset.3112058722
Line 460, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 30504262689 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x9d9ed894) == 0x6
UVM_INFO @ 30504262689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.csrng_stress_all_with_rand_reset.37182004
Line 287, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10001676040 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout csrng_reg_block.ctrl.enable (addr=0x89634b94) == 0x6
UVM_INFO @ 10001676040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference.
has 4 failures:
6.csrng_stress_all_with_rand_reset.3481320471
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 17152490 PS + 14
Verilog Stack Trace:
11.csrng_stress_all_with_rand_reset.387854499
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all_with_rand_reset/latest/run.log
xmsim: *E,TRNULLID: NULL pointer dereference.
File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 283, pos = 18
Scope: worklib.csrng_env_pkg::csrng_scoreboard@4984_4.process_tl_access
Time: 7234330 PS + 11
Verilog Stack Trace:
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed
has 4 failures:
274.csrng_err.143044411
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/274.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1768555 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1768555 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1768555 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 1768555 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 1768555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
353.csrng_err.3894038696
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/353.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 32090964 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 32090964 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 32090964 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
UVM_ERROR @ 32090964 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
UVM_INFO @ 32090964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 2 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed
has 3 failures:
35.csrng_err.2064585453
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/35.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 4956251 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 4956251 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 4956251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
206.csrng_err.545992530
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/206.csrng_err/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 6764107 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
UVM_ERROR @ 6764107 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 6764107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
has 2 failures:
17.csrng_stress_all.1330964603
Line 272, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/17.csrng_stress_all/latest/run.log
UVM_ERROR @ 1038346077 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 1038346077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.csrng_stress_all.101785057
Line 253, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log
UVM_ERROR @ 57036466 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 57036466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:573) scoreboard [scoreboard] Invalid csrng_acmd: *
has 2 failures:
19.csrng_stress_all_with_rand_reset.2553871718
Line 378, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/19.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 14723960160 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
UVM_INFO @ 14723960160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.csrng_stress_all_with_rand_reset.3176515157
Line 381, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/26.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 10018223144 ps: (csrng_scoreboard.sv:573) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x6
UVM_INFO @ 10018223144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started
has 1 failures:
32.csrng_stress_all_with_rand_reset.1104228004
Line 229, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1204218 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
UVM_INFO @ 1204218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:144) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq
has 1 failures:
36.csrng_stress_all.4261232320
Line 262, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
UVM_ERROR @ 215220335 ps: (csrng_scoreboard.sv:144) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
UVM_INFO @ 215220335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---