V1 |
smoke |
csrng_smoke |
14.000s |
62.596us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
csrng_csr_hw_reset |
9.000s |
20.196us |
5 |
5 |
100.00 |
V1 |
csr_rw |
csrng_csr_rw |
14.000s |
24.874us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
csrng_csr_bit_bash |
18.000s |
202.296us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
csrng_csr_aliasing |
17.000s |
42.179us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
csrng_csr_mem_rw_with_rand_reset |
23.000s |
22.434us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
csrng_csr_rw |
14.000s |
24.874us |
20 |
20 |
100.00 |
|
|
csrng_csr_aliasing |
17.000s |
42.179us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
interrupts |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
V2 |
alerts |
csrng_alert |
6.000s |
88.396us |
500 |
500 |
100.00 |
V2 |
err |
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
V2 |
cmds |
csrng_cmds |
1.183m |
4.218ms |
50 |
50 |
100.00 |
V2 |
life cycle |
csrng_cmds |
1.183m |
4.218ms |
50 |
50 |
100.00 |
V2 |
stress_all |
csrng_stress_all |
7.633m |
19.138ms |
50 |
50 |
100.00 |
V2 |
intr_test |
csrng_intr_test |
9.000s |
18.298us |
50 |
50 |
100.00 |
V2 |
alert_test |
csrng_alert_test |
8.000s |
17.315us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
csrng_tl_errors |
17.000s |
66.043us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
csrng_tl_errors |
17.000s |
66.043us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
csrng_csr_hw_reset |
9.000s |
20.196us |
5 |
5 |
100.00 |
|
|
csrng_csr_rw |
14.000s |
24.874us |
20 |
20 |
100.00 |
|
|
csrng_csr_aliasing |
17.000s |
42.179us |
5 |
5 |
100.00 |
|
|
csrng_same_csr_outstanding |
16.000s |
34.518us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
csrng_csr_hw_reset |
9.000s |
20.196us |
5 |
5 |
100.00 |
|
|
csrng_csr_rw |
14.000s |
24.874us |
20 |
20 |
100.00 |
|
|
csrng_csr_aliasing |
17.000s |
42.179us |
5 |
5 |
100.00 |
|
|
csrng_same_csr_outstanding |
16.000s |
34.518us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
1440 |
1440 |
100.00 |
V2S |
tl_intg_err |
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
|
|
csrng_tl_intg_err |
14.000s |
92.280us |
20 |
20 |
100.00 |
V2S |
sec_cm_config_regwen |
csrng_regwen |
14.000s |
20.790us |
50 |
50 |
100.00 |
|
|
csrng_csr_rw |
14.000s |
24.874us |
20 |
20 |
100.00 |
V2S |
sec_cm_config_mubi |
csrng_alert |
6.000s |
88.396us |
500 |
500 |
100.00 |
V2S |
sec_cm_intersig_mubi |
csrng_stress_all |
7.633m |
19.138ms |
50 |
50 |
100.00 |
V2S |
sec_cm_main_sm_fsm_sparse |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_update_fsm_sparse |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_blk_enc_fsm_sparse |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_outblk_fsm_sparse |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_gen_cmd_ctr_redun |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_drbg_upd_ctr_redun |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_drbg_gen_ctr_redun |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_ctrl_mubi |
csrng_alert |
6.000s |
88.396us |
500 |
500 |
100.00 |
V2S |
sec_cm_main_sm_ctr_local_esc |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
V2S |
sec_cm_constants_lc_gated |
csrng_stress_all |
7.633m |
19.138ms |
50 |
50 |
100.00 |
V2S |
sec_cm_sw_genbits_bus_consistency |
csrng_alert |
6.000s |
88.396us |
500 |
500 |
100.00 |
V2S |
sec_cm_tile_link_bus_integrity |
csrng_tl_intg_err |
14.000s |
92.280us |
20 |
20 |
100.00 |
V2S |
sec_cm_aes_cipher_fsm_sparse |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_aes_cipher_fsm_redun |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
V2S |
sec_cm_aes_cipher_ctrl_sparse |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
V2S |
sec_cm_aes_cipher_fsm_local_esc |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
V2S |
sec_cm_aes_cipher_ctr_redun |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
|
|
csrng_sec_cm |
6.000s |
83.721us |
5 |
5 |
100.00 |
V2S |
sec_cm_aes_cipher_data_reg_local_esc |
csrng_intr |
9.000s |
71.756us |
200 |
200 |
100.00 |
|
|
csrng_err |
5.000s |
31.636us |
500 |
500 |
100.00 |
V2S |
|
TOTAL |
|
|
75 |
75 |
100.00 |
V3 |
stress_all_with_rand_reset |
csrng_stress_all_with_rand_reset |
1.540h |
118.971ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
1670 |
1670 |
100.00 |