CSRNG Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: XCELIUM

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	28.000s	35.373us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.533m	14.203us	5	5	100.00
V1	csr_rw	csrng_csr_rw	59.000s	194.549us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	2.983m	7.457ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	35.000s	41.313us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.133m	91.328us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	59.000s	194.549us	20	20	100.00
		csrng_csr_aliasing	35.000s	41.313us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.450m	123.557us	200	200	100.00
V2	alerts	csrng_alert	2.733m	956.853us	500	500	100.00
V2	err	csrng_err	1.833m	31.212us	498	500	99.60
V2	cmds	csrng_cmds	11.683m	8.159ms	50	50	100.00
V2	life cycle	csrng_cmds	11.683m	8.159ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.683m	153.315ms	47	50	94.00
V2	intr_test	csrng_intr_test	58.000s	55.987us	50	50	100.00
V2	alert_test	csrng_alert_test	22.000s	17.758us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	1.567m	704.529us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	1.567m	704.529us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.533m	14.203us	5	5	100.00
		csrng_csr_rw	59.000s	194.549us	20	20	100.00
		csrng_csr_aliasing	35.000s	41.313us	5	5	100.00
		csrng_same_csr_outstanding	57.000s	25.132us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.533m	14.203us	5	5	100.00
		csrng_csr_rw	59.000s	194.549us	20	20	100.00
		csrng_csr_aliasing	35.000s	41.313us	5	5	100.00
		csrng_same_csr_outstanding	57.000s	25.132us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	8.000s	240.398us	5	5	100.00
		csrng_tl_intg_err	1.567m	492.477us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	22.000s	30.030us	50	50	100.00
		csrng_csr_rw	59.000s	194.549us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.733m	956.853us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.683m	153.315ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.733m	956.853us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.683m	153.315ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.733m	956.853us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.567m	492.477us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
		csrng_sec_cm	8.000s	240.398us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.450m	123.557us	200	200	100.00
		csrng_err	1.833m	31.212us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.600m	2.309ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.34	98.37	96.16	99.09	96.70	91.84	100.00	97.41	90.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.74372167301044474137753030955682091655425281448626021202132657705396178690747
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110135455 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 110135455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.41712158591981690557743102218991903637218018986915763681669496541834369923702
    Line 100, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3082085815 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3082085815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 32.csrng_stress_all.104359298346171977015268386860076124942340908186023993357332675553564264262688
    Line 161, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/32.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3074195006 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3074195006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.csrng_stress_all.26948386411508093730972078102315060036986555443161844258520439874492933186885
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 8643243430 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8643243430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

5.csrng_stress_all_with_rand_reset.39921984511569425992688182107142678310340232181781972109800662054294173961590
Line 100, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  19898094 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @  19898094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.csrng_stress_all_with_rand_reset.32735004734428205014782902482001221291459938760107459740578337567857550197481
Line 103, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  10270564 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  10270564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

130.csrng_err.64838792161705700228521858350383308929871078219710442836335375035910427029523
Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/130.csrng_err/latest/run.log

  UVM_ERROR @   5070197 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5070197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

449.csrng_err.44869064107313361583670072283201563844070645687456840482670286560703820111172
Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_14/csrng-sim-xcelium/449.csrng_err/latest/run.log

  UVM_ERROR @   3343949 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   3343949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---