CSRNG Simulation Results

Sunday September 17 2023 19:02:18 UTC

GitHub Revision: `3451d3b85`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 266892513

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	23.351us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	37.253us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	137.554us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	20.000s	1.436ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	13.000s	17.899us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	10.000s	27.556us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	137.554us	20	20	100.00
		csrng_csr_aliasing	13.000s	17.899us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	14.000s	44.930us	200	200	100.00
V2	alerts	csrng_alert	20.000s	30.898us	500	500	100.00
V2	err	csrng_err	19.000s	19.552us	487	500	97.40
V2	cmds	csrng_cmds	10.883m	57.124ms	50	50	100.00
V2	life cycle	csrng_cmds	10.883m	57.124ms	50	50	100.00
V2	stress_all	csrng_stress_all	23.783m	42.227ms	49	50	98.00
V2	intr_test	csrng_intr_test	4.000s	49.503us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	38.986us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	14.000s	111.557us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	14.000s	111.557us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	37.253us	5	5	100.00
		csrng_csr_rw	4.000s	137.554us	20	20	100.00
		csrng_csr_aliasing	13.000s	17.899us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	497.358us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	37.253us	5	5	100.00
		csrng_csr_rw	4.000s	137.554us	20	20	100.00
		csrng_csr_aliasing	13.000s	17.899us	5	5	100.00
		csrng_same_csr_outstanding	13.000s	497.358us	20	20	100.00
V2		TOTAL			1426	1440	99.03
V2S	tl_intg_err	csrng_sec_cm	6.000s	91.701us	5	5	100.00
		csrng_tl_intg_err	17.000s	210.521us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	13.000s	20.145us	50	50	100.00
		csrng_csr_rw	4.000s	137.554us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	20.000s	30.898us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	23.783m	42.227ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	20.000s	30.898us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	23.783m	42.227ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	20.000s	30.898us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	210.521us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
		csrng_sec_cm	6.000s	91.701us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	14.000s	44.930us	200	200	100.00
		csrng_err	19.000s	19.552us	487	500	97.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.814h	455.205ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			1641	1670	98.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
92.77	93.24	84.31	95.35	86.47	92.29	100.00	97.50	95.52

Failure Buckets

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,193): Assertion DataKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

12.csrng_err.3650446866
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 13249660 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @  13249660 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @  13249660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

73.csrng_err.4287965767
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/73.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,193): (time 2237083 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_prim_fifo_sync_rcstage.DataKnown_A has failed
  UVM_ERROR @   2237083 ps: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2237083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_*/rtl/prim_arbiter_ppc.sv,139): Assertion ValidKnown_A has failed has 6 failures:

Test csrng_err has 6 failures.

63.csrng_err.2562277320
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/63.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 5183117 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 5183117 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 5183117 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   5183117 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   5183117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

110.csrng_err.3655150926
Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/110.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,139): (time 1885023 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.ValidKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,140): (time 1885023 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.GrantKnown_A has failed
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv,141): (time 1885023 PS) Assertion tb.dut.u_csrng_core.u_prim_arbiter_ppc_updblk_arb.IdxKnown_A has failed
  UVM_ERROR @   1885023 ps: (prim_arbiter_ppc.sv:139) [ASSERT FAILED] ValidKnown_A
  UVM_INFO @   1885023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]

... and 4 more failures.

UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 5 failures:

Test csrng_stress_all_with_rand_reset has 5 failures.

5.csrng_stress_all_with_rand_reset.1846230312
Line 846, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/5.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 91948626866 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 91948626866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.csrng_stress_all_with_rand_reset.3306944578
Line 987, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 97174964488 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 97174964488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Job csrng-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 11.csrng_stress_all_with_rand_reset.752502082
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:99ff8337-af53-4c47-b2b5-208244248bca
```
  - 30.csrng_stress_all_with_rand_reset.2092538050
    Log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/30.csrng_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:70cd6ac6-f225-49d2-9b36-95f41de1f9df
```
  - ... and 1 more failures.
Exit reason: Error: User command failed UVM_FATAL (csrng_scoreboard.sv:584) scoreboard [scoreboard] Invalid csrng_acmd: * has 3 failures:
- Test csrng_stress_all_with_rand_reset has 3 failures.
  - 12.csrng_stress_all_with_rand_reset.555972458
    Line 448, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/12.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 90763817212 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x7
  UVM_INFO @ 90763817212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.csrng_stress_all_with_rand_reset.3744135864
    Line 576, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/20.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 856216719360 ps: (csrng_scoreboard.sv:584) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Invalid csrng_acmd: 0x0
  UVM_INFO @ 856216719360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,TRNULLID: NULL pointer dereference. has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

14.csrng_stress_all_with_rand_reset.2213299150
Line 234, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/14.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 11486401 PS + 12
  Verilog Stack Trace:

15.csrng_stress_all_with_rand_reset.2904640136
Line 237, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/15.csrng_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,TRNULLID: NULL pointer dereference.
            File: /workspace/default/src/lowrisc_dv_csrng_env_0.1/csrng_scoreboard.sv, line = 294, pos = 18
           Scope: worklib.csrng_env_pkg::csrng_scoreboard@4985_4.process_tl_access
            Time: 50204509 PS + 11
  Verilog Stack Trace:

... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (csrng_scoreboard.sv:155) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 11.csrng_stress_all.2825475437
    Line 273, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1871632462 ps: (csrng_scoreboard.sv:155) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1871632462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 32.csrng_stress_all_with_rand_reset.2994322967
    Line 397, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/32.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 78265030591 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @ 78265030591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 492.csrng_err.3716247078
    Line 255, in log /container/opentitan-public/scratch/os_regression/csrng-sim-xcelium/492.csrng_err/latest/run.log
```
  UVM_ERROR @  24483541 ps: (csr_utils_pkg.sv:459) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  24483541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```