V1 |
smoke |
edn_smoke |
1.030s |
32.178us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
edn_csr_hw_reset |
0.920s |
15.990us |
5 |
5 |
100.00 |
V1 |
csr_rw |
edn_csr_rw |
0.930s |
28.296us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
edn_csr_bit_bash |
3.650s |
343.714us |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
edn_csr_aliasing |
1.430s |
69.710us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
edn_csr_mem_rw_with_rand_reset |
2.050s |
37.648us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
edn_csr_rw |
0.930s |
28.296us |
20 |
20 |
100.00 |
|
|
edn_csr_aliasing |
1.430s |
69.710us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
V2 |
firmware |
edn_genbits |
1.450s |
447.050us |
50 |
50 |
100.00 |
V2 |
csrng_commands |
edn_genbits |
1.450s |
447.050us |
50 |
50 |
100.00 |
V2 |
genbits |
edn_genbits |
1.450s |
447.050us |
50 |
50 |
100.00 |
V2 |
interrupts |
edn_intr |
1.220s |
19.361us |
50 |
50 |
100.00 |
V2 |
alerts |
edn_alert |
1.070s |
32.235us |
50 |
50 |
100.00 |
V2 |
errs |
edn_err |
1.170s |
26.049us |
50 |
50 |
100.00 |
V2 |
disable |
edn_disable |
0.920s |
14.165us |
49 |
50 |
98.00 |
|
|
edn_disable_auto_req_mode |
1.120s |
139.377us |
50 |
50 |
100.00 |
V2 |
stress_all |
edn_stress_all |
4.010s |
288.671us |
50 |
50 |
100.00 |
V2 |
intr_test |
edn_intr_test |
0.940s |
18.212us |
50 |
50 |
100.00 |
V2 |
alert_test |
edn_alert_test |
2.140s |
219.656us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
edn_tl_errors |
4.950s |
295.125us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
edn_tl_errors |
4.950s |
295.125us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
edn_csr_hw_reset |
0.920s |
15.990us |
5 |
5 |
100.00 |
|
|
edn_csr_rw |
0.930s |
28.296us |
20 |
20 |
100.00 |
|
|
edn_csr_aliasing |
1.430s |
69.710us |
5 |
5 |
100.00 |
|
|
edn_same_csr_outstanding |
1.460s |
37.266us |
20 |
20 |
100.00 |
V2 |
tl_d_partial_access |
edn_csr_hw_reset |
0.920s |
15.990us |
5 |
5 |
100.00 |
|
|
edn_csr_rw |
0.930s |
28.296us |
20 |
20 |
100.00 |
|
|
edn_csr_aliasing |
1.430s |
69.710us |
5 |
5 |
100.00 |
|
|
edn_same_csr_outstanding |
1.460s |
37.266us |
20 |
20 |
100.00 |
V2 |
|
TOTAL |
|
|
489 |
490 |
99.80 |
V2S |
tl_intg_err |
edn_sec_cm |
5.510s |
352.847us |
5 |
5 |
100.00 |
|
|
edn_tl_intg_err |
2.990s |
135.899us |
20 |
20 |
100.00 |
V2S |
sec_cm_config_regwen |
edn_regwen |
0.940s |
186.840us |
10 |
10 |
100.00 |
V2S |
sec_cm_config_mubi |
edn_alert |
1.070s |
32.235us |
50 |
50 |
100.00 |
V2S |
sec_cm_main_sm_fsm_sparse |
edn_sec_cm |
5.510s |
352.847us |
5 |
5 |
100.00 |
V2S |
sec_cm_ack_sm_fsm_sparse |
edn_sec_cm |
5.510s |
352.847us |
5 |
5 |
100.00 |
V2S |
sec_cm_ctr_redun |
edn_sec_cm |
5.510s |
352.847us |
5 |
5 |
100.00 |
V2S |
sec_cm_main_sm_ctr_local_esc |
edn_alert |
1.070s |
32.235us |
50 |
50 |
100.00 |
|
|
edn_sec_cm |
5.510s |
352.847us |
5 |
5 |
100.00 |
V2S |
sec_cm_cs_rdata_bus_consistency |
edn_alert |
1.070s |
32.235us |
50 |
50 |
100.00 |
V2S |
sec_cm_tile_link_bus_integrity |
edn_tl_intg_err |
2.990s |
135.899us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
35 |
35 |
100.00 |
V3 |
stress_all_with_rand_reset |
edn_stress_all_with_rand_reset |
48.208m |
138.233ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
679 |
680 |
99.85 |