EDN Simulation Results

Tuesday May 30 2023 07:03:17 UTC

GitHub Revision: f8b3c19a2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1284268927

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.980s 13.580us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.860s 47.576us 5 5 100.00
V1 csr_rw edn_csr_rw 1.040s 49.851us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.800s 1.476ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.360s 150.574us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.910s 246.946us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.040s 49.851us 20 20 100.00
edn_csr_aliasing 1.360s 150.574us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.540s 46.656us 50 50 100.00
V2 csrng_commands edn_genbits 1.540s 46.656us 50 50 100.00
V2 genbits edn_genbits 1.540s 46.656us 50 50 100.00
V2 interrupts edn_intr 1.190s 20.844us 50 50 100.00
V2 alerts edn_alert 1.070s 18.652us 50 50 100.00
V2 errs edn_err 1.100s 25.005us 50 50 100.00
V2 disable edn_disable 0.970s 14.481us 50 50 100.00
edn_disable_auto_req_mode 1.140s 36.840us 50 50 100.00
V2 stress_all edn_stress_all 4.400s 2.232ms 50 50 100.00
V2 intr_test edn_intr_test 0.930s 25.180us 50 50 100.00
V2 alert_test edn_alert_test 1.450s 51.557us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.630s 146.876us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.630s 146.876us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.860s 47.576us 5 5 100.00
edn_csr_rw 1.040s 49.851us 20 20 100.00
edn_csr_aliasing 1.360s 150.574us 5 5 100.00
edn_same_csr_outstanding 1.440s 142.476us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.860s 47.576us 5 5 100.00
edn_csr_rw 1.040s 49.851us 20 20 100.00
edn_csr_aliasing 1.360s 150.574us 5 5 100.00
edn_same_csr_outstanding 1.440s 142.476us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err edn_sec_cm 6.850s 449.402us 5 5 100.00
edn_tl_intg_err 21.110s 1.858ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 15.673us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.070s 18.652us 50 50 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.850s 449.402us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.850s 449.402us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.850s 449.402us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.070s 18.652us 50 50 100.00
edn_sec_cm 6.850s 449.402us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.070s 18.652us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 21.110s 1.858ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 42.477m 778.799ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 680 680 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.36 99.03 94.43 96.79 73.03 98.62 99.77 98.84

Past Results