EDN Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.560s	18.379us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.480s	35.884us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.420s	19.673us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	8.940s	611.631us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.410s	383.122us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.260s	65.684us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.420s	19.673us	20	20	100.00
		edn_csr_aliasing	2.410s	383.122us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	7.730s	1.091ms	300	300	100.00
V2	csrng_commands	edn_genbits	7.730s	1.091ms	300	300	100.00
V2	genbits	edn_genbits	7.730s	1.091ms	300	300	100.00
V2	interrupts	edn_intr	1.810s	22.104us	50	50	100.00
V2	alerts	edn_alert	2.690s	340.735us	200	200	100.00
V2	errs	edn_err	2.160s	33.089us	100	100	100.00
V2	disable	edn_disable	1.430s	15.782us	50	50	100.00
		edn_disable_auto_req_mode	2.500s	68.738us	50	50	100.00
V2	stress_all	edn_stress_all	11.090s	376.617us	50	50	100.00
V2	intr_test	edn_intr_test	1.380s	16.245us	50	50	100.00
V2	alert_test	edn_alert_test	1.570s	25.503us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	6.650s	517.976us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	6.650s	517.976us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.480s	35.884us	5	5	100.00
		edn_csr_rw	1.420s	19.673us	20	20	100.00
		edn_csr_aliasing	2.410s	383.122us	5	5	100.00
		edn_same_csr_outstanding	2.140s	126.801us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.480s	35.884us	5	5	100.00
		edn_csr_rw	1.420s	19.673us	20	20	100.00
		edn_csr_aliasing	2.410s	383.122us	5	5	100.00
		edn_same_csr_outstanding	2.140s	126.801us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	14.100s	1.143ms	5	5	100.00
		edn_tl_intg_err	4.000s	135.841us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.530s	16.808us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.690s	340.735us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	14.100s	1.143ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	14.100s	1.143ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	14.100s	1.143ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	14.100s	1.143ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.690s	340.735us	200	200	100.00
		edn_sec_cm	14.100s	1.143ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.690s	340.735us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.000s	135.841us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	46.747m	689.606ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1130	1130	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.61	98.25	93.91	97.02	91.86	96.37	99.77	92.06

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