EDN Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.500s	18.049us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.380s	15.534us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.410s	28.940us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.130s	134.838us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.270s	65.172us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.250s	104.075us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.410s	28.940us	20	20	100.00
		edn_csr_aliasing	2.270s	65.172us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.166m	2.932ms	290	300	96.67
V2	csrng_commands	edn_genbits	1.166m	2.932ms	290	300	96.67
V2	genbits	edn_genbits	1.166m	2.932ms	290	300	96.67
V2	interrupts	edn_intr	1.770s	20.498us	50	50	100.00
V2	alerts	edn_alert	2.160s	260.870us	200	200	100.00
V2	errs	edn_err	1.880s	100.508us	100	100	100.00
V2	disable	edn_disable	1.440s	15.152us	50	50	100.00
		edn_disable_auto_req_mode	2.110s	46.742us	50	50	100.00
V2	stress_all	edn_stress_all	7.830s	274.662us	50	50	100.00
V2	intr_test	edn_intr_test	1.320s	13.110us	50	50	100.00
V2	alert_test	edn_alert_test	5.270s	266.001us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.330s	98.062us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.330s	98.062us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.380s	15.534us	5	5	100.00
		edn_csr_rw	1.410s	28.940us	20	20	100.00
		edn_csr_aliasing	2.270s	65.172us	5	5	100.00
		edn_same_csr_outstanding	2.010s	34.258us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.380s	15.534us	5	5	100.00
		edn_csr_rw	1.410s	28.940us	20	20	100.00
		edn_csr_aliasing	2.270s	65.172us	5	5	100.00
		edn_same_csr_outstanding	2.010s	34.258us	20	20	100.00
V2		TOTAL			930	940	98.94
V2S	tl_intg_err	edn_sec_cm	12.100s	1.026ms	5	5	100.00
		edn_tl_intg_err	3.540s	241.952us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.540s	18.534us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.160s	260.870us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	12.100s	1.026ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	12.100s	1.026ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	12.100s	1.026ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	12.100s	1.026ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.160s	260.870us	200	200	100.00
		edn_sec_cm	12.100s	1.026ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.160s	260.870us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.540s	241.952us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.426h	10.000s	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1098	1130	97.17

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.90	98.23	93.91	97.02	93.02	96.33	99.77	92.99

Failure Buckets

Job timed out after * minutes has 21 failures:
- Test edn_stress_all_with_rand_reset has 21 failures.
  - 0.edn_stress_all_with_rand_reset.59570230828072606527802510500531575399020575294300538872087428552846422089324
    Log /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 5.edn_stress_all_with_rand_reset.9359920426731333761551342384443045370388830707825035994117457971389448537717
    Log /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 19 more failures.

Job returned non-zero exit code has 10 failures:

Test edn_genbits has 10 failures.

160.edn_genbits.109781886797335462480242747071712141677704641842142863618145956624009771264348
Log /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/160.edn_genbits/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

224.edn_genbits.46759794607877703997523169242533853398950580326886633485165874301705304767785
Log /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/224.edn_genbits/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 11:28 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 8 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 4.edn_stress_all_with_rand_reset.63446424199589214521306590885440417687675232081473375269011463763548382032300
    Line 387, in log /workspaces/repo/scratch/os_regression_2024_10_14/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```