Testbench Group List
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Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
424 431 98.38 424 431 98.38 1


Total groups in report: 22
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 12 15 80.00 100.00 1 100 1 1 64 64
tb.dut.u_edn_cov_if::edn_cfg_cg 27 33 81.82 81.82 1 100 1 1 64 64
tb.dut.u_edn_cov_if::edn_error_cg 8 9 88.89 88.89 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 13 14 92.86 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1} 14 14 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1} 14 14 100.00 1 100 1 0 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1} 20 20 100.00 1 100 1 0 64 64
csrng_agent_pkg::device_cmd_cg 51 51 100.00 100.00 1 100 1 1 64 64
csrng_agent_pkg::device_genbits_cg 14 14 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg 6 6 100.00 100.00 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_edn_cov_if::edn_alert_cg 5 5 100.00 100.00 1 100 1 1 64 64
tb.dut.u_edn_cov_if::edn_cs_cmds_cg 14 14 100.00 100.00 1 100 1 1 64 64
tb.dut.u_edn_cov_if::edn_endpoints_cg 3 3 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_if_proxy::onehot_fault_cg 3 3 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::req_ack_cg 3 3 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::valid_ready_cg 4 4 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::pending_req_on_rst_cg 2 2 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%