Summary for Variable cp_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_mode
Excluded/Illegal bins
NAME | COUNT | STATUS |
both |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
boot_req_mode |
64 |
1 |
|
|
T1 |
1 |
|
T31 |
1 |
|
T51 |
1 |
auto_req_mode |
22 |
1 |
|
|
T10 |
1 |
|
T14 |
1 |
|
T68 |
1 |
sw_mode |
2595 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T6 |
9 |
Summary for Variable cp_num_boot_reqs
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_boot_reqs
Excluded/Illegal bins
NAME | COUNT | STATUS |
zero |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
multiple |
74 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
single |
34 |
1 |
|
|
T30 |
1 |
|
T67 |
1 |
|
T73 |
1 |
Summary for Variable cp_num_endpoints
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
7 |
0 |
7 |
100.00 |
Automatically Generated Bins for cp_num_endpoints
Excluded/Illegal bins
NAME | COUNT | STATUS |
zero |
0 |
Excluded |
[auto[0]] |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
1048 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
1 |
auto[2] |
108 |
1 |
|
|
T2 |
1 |
|
T259 |
1 |
|
T260 |
66 |
auto[3] |
160 |
1 |
|
|
T6 |
9 |
|
T261 |
11 |
|
T262 |
3 |
auto[4] |
142 |
1 |
|
|
T241 |
10 |
|
T263 |
37 |
|
T264 |
60 |
auto[5] |
86 |
1 |
|
|
T26 |
27 |
|
T11 |
1 |
|
T265 |
57 |
auto[6] |
1 |
1 |
|
|
T266 |
1 |
|
- |
- |
|
- |
- |
auto[7] |
1136 |
1 |
|
|
T20 |
1 |
|
T37 |
11 |
|
T25 |
35 |
Summary for Cross cr_num_endpoints_mode
Samples crossed: cp_num_endpoints cp_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
21 |
5 |
16 |
76.19 |
5 |
Automatically Generated Cross Bins for cr_num_endpoints_mode
Uncovered bins
cp_num_endpoints | cp_mode | COUNT | AT LEAST | NUMBER | STATUS |
[auto[2]] |
[auto_req_mode] |
0 |
1 |
1 |
|
[auto[3]] |
[boot_req_mode , auto_req_mode] |
-- |
-- |
2 |
|
[auto[6]] |
[boot_req_mode] |
0 |
1 |
1 |
|
[auto[6]] |
[sw_mode] |
0 |
1 |
1 |
|
Excluded/Illegal bins
cp_num_endpoints | cp_mode | COUNT | STATUS | |
[auto[0]] |
[boot_req_mode , auto_req_mode , sw_mode] |
-- |
Excluded |
(3 bins) |
Covered bins
cp_num_endpoints | cp_mode | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
boot_req_mode |
53 |
1 |
|
|
T1 |
1 |
|
T31 |
1 |
|
T51 |
1 |
auto[1] |
auto_req_mode |
16 |
1 |
|
|
T10 |
1 |
|
T14 |
1 |
|
T68 |
1 |
auto[1] |
sw_mode |
979 |
1 |
|
|
T3 |
1 |
|
T19 |
1 |
|
T62 |
1 |
auto[2] |
boot_req_mode |
1 |
1 |
|
|
T259 |
1 |
|
- |
- |
|
- |
- |
auto[2] |
sw_mode |
107 |
1 |
|
|
T2 |
1 |
|
T260 |
66 |
|
T267 |
39 |
auto[3] |
sw_mode |
160 |
1 |
|
|
T6 |
9 |
|
T261 |
11 |
|
T262 |
3 |
auto[4] |
boot_req_mode |
3 |
1 |
|
|
T268 |
1 |
|
T269 |
1 |
|
T270 |
1 |
auto[4] |
auto_req_mode |
1 |
1 |
|
|
T271 |
1 |
|
- |
- |
|
- |
- |
auto[4] |
sw_mode |
138 |
1 |
|
|
T241 |
10 |
|
T263 |
37 |
|
T264 |
60 |
auto[5] |
boot_req_mode |
1 |
1 |
|
|
T272 |
1 |
|
- |
- |
|
- |
- |
auto[5] |
auto_req_mode |
1 |
1 |
|
|
T11 |
1 |
|
- |
- |
|
- |
- |
auto[5] |
sw_mode |
84 |
1 |
|
|
T26 |
27 |
|
T265 |
57 |
|
- |
- |
auto[6] |
auto_req_mode |
1 |
1 |
|
|
T266 |
1 |
|
- |
- |
|
- |
- |
auto[7] |
boot_req_mode |
6 |
1 |
|
|
T38 |
1 |
|
T90 |
1 |
|
T95 |
1 |
auto[7] |
auto_req_mode |
3 |
1 |
|
|
T91 |
1 |
|
T13 |
1 |
|
T273 |
1 |
auto[7] |
sw_mode |
1127 |
1 |
|
|
T20 |
1 |
|
T37 |
11 |
|
T25 |
35 |