Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	516476	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4577998

1

T1

4

T2

11

T3

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1322905	1			T1	1		T2	37		T3	71
values[0x0]	1747941	1			T1	1		T2	4		T3	12
values[0x1]	2023628	1			T1	4		T2	8		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	250853	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4843621

1

T1

4

T2

19

T3

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20281	1			T37	1		T25	137		T26	228
valid_sources[0x01]	20150	1			T6	13		T7	3		T37	4
valid_sources[0x02]	21197	1			T3	1		T7	1		T37	3
valid_sources[0x03]	18783	1			T3	1		T20	9		T17	1
valid_sources[0x04]	19023	1			T21	2		T37	2		T25	140
valid_sources[0x05]	18777	1			T37	2		T25	118		T26	925
valid_sources[0x06]	19000	1			T6	10		T37	4		T25	127
valid_sources[0x07]	20530	1			T3	1		T37	2		T8	3
valid_sources[0x08]	21554	1			T6	1		T37	6		T25	124
valid_sources[0x09]	20405	1			T37	1		T8	2		T25	128
valid_sources[0x0a]	18052	1			T37	4		T25	136		T26	55
valid_sources[0x0b]	17560	1			T5	1		T6	8		T37	5
valid_sources[0x0c]	19998	1			T37	4		T25	134		T26	346
valid_sources[0x0d]	22170	1			T6	4		T21	2		T37	2
valid_sources[0x0e]	18910	1			T37	2		T8	1		T25	116
valid_sources[0x0f]	20860	1			T37	4		T25	135		T26	1
valid_sources[0x10]	19733	1			T37	4		T25	125		T174	1
valid_sources[0x11]	20379	1			T6	2		T37	4		T25	115
valid_sources[0x12]	20033	1			T37	7		T25	128		T9	1
valid_sources[0x13]	21198	1			T17	1		T37	4		T25	120
valid_sources[0x14]	18536	1			T8	1		T25	146		T26	115
valid_sources[0x15]	19563	1			T3	4		T6	3		T37	2
valid_sources[0x16]	20602	1			T37	3		T8	1		T25	126
valid_sources[0x17]	20805	1			T4	1		T37	4		T25	130
valid_sources[0x18]	18035	1			T37	4		T8	2		T25	139
valid_sources[0x19]	19310	1			T17	1		T37	2		T8	1
valid_sources[0x1a]	19409	1			T37	5		T25	113		T26	3
valid_sources[0x1b]	22175	1			T6	1		T20	10		T37	1
valid_sources[0x1c]	19867	1			T4	1		T6	5		T37	2
valid_sources[0x1d]	19892	1			T37	6		T8	1		T25	134
valid_sources[0x1e]	20201	1			T5	2		T37	4		T25	148
valid_sources[0x1f]	20449	1			T6	1		T37	3		T25	113
valid_sources[0x20]	17999	1			T37	2		T25	126		T26	243
valid_sources[0x21]	20255	1			T6	1		T37	3		T25	139
valid_sources[0x22]	22105	1			T3	1		T6	1		T37	6
valid_sources[0x23]	21352	1			T6	5		T17	1		T37	5
valid_sources[0x24]	19952	1			T6	10		T37	2		T8	1
valid_sources[0x25]	20550	1			T4	3		T6	4		T17	1
valid_sources[0x26]	18944	1			T17	1		T37	2		T25	108
valid_sources[0x27]	20046	1			T3	1		T37	6		T25	125
valid_sources[0x28]	18370	1			T20	3		T37	6		T25	122
valid_sources[0x29]	19504	1			T3	4		T6	4		T37	4
valid_sources[0x2a]	17639	1			T17	1		T37	2		T25	126
valid_sources[0x2b]	19273	1			T3	1		T37	4		T25	131
valid_sources[0x2c]	19655	1			T6	7		T37	1		T25	149
valid_sources[0x2d]	21041	1			T17	1		T8	3		T25	144
valid_sources[0x2e]	19732	1			T6	1		T37	2		T8	2
valid_sources[0x2f]	20644	1			T37	2		T25	110		T26	4
valid_sources[0x30]	18769	1			T2	1		T5	3		T8	1
valid_sources[0x31]	20363	1			T37	4		T25	138		T26	209
valid_sources[0x32]	20884	1			T7	2		T37	2		T25	140
valid_sources[0x33]	20630	1			T3	2		T6	3		T37	5
valid_sources[0x34]	19308	1			T6	1		T20	1		T17	1
valid_sources[0x35]	18913	1			T7	2		T17	1		T37	1
valid_sources[0x36]	19573	1			T37	2		T50	1		T25	139
valid_sources[0x37]	19120	1			T37	5		T25	125		T26	453
valid_sources[0x38]	19766	1			T7	1		T37	1		T25	117
valid_sources[0x39]	17862	1			T6	3		T25	151		T26	188
valid_sources[0x3a]	22350	1			T6	8		T20	6		T21	1
valid_sources[0x3b]	18094	1			T37	3		T25	140		T26	273
valid_sources[0x3c]	17459	1			T5	2		T21	2		T37	8
valid_sources[0x3d]	18722	1			T6	5		T37	4		T8	1
valid_sources[0x3e]	20058	1			T37	6		T25	136		T26	171
valid_sources[0x3f]	18824	1			T7	4		T17	1		T37	5
valid_sources[0x40]	20380	1			T3	1		T6	1		T7	1
valid_sources[0x41]	19296	1			T3	3		T6	1		T37	2
valid_sources[0x42]	19898	1			T2	1		T17	1		T37	2
valid_sources[0x43]	20414	1			T6	6		T37	4		T25	153
valid_sources[0x44]	20725	1			T6	3		T37	3		T25	137
valid_sources[0x45]	20452	1			T6	2		T7	1		T37	2
valid_sources[0x46]	20609	1			T37	5		T51	1		T25	144
valid_sources[0x47]	20991	1			T3	1		T37	2		T25	121
valid_sources[0x48]	18559	1			T6	1		T25	119		T26	153
valid_sources[0x49]	21432	1			T5	2		T6	2		T37	3
valid_sources[0x4a]	20365	1			T7	4		T37	2		T25	145
valid_sources[0x4b]	19950	1			T6	2		T25	121		T174	1
valid_sources[0x4c]	21164	1			T6	6		T37	1		T25	133
valid_sources[0x4d]	20328	1			T6	1		T37	1		T25	144
valid_sources[0x4e]	19295	1			T5	1		T6	5		T25	161
valid_sources[0x4f]	19167	1			T6	1		T17	1		T37	3
valid_sources[0x50]	20632	1			T37	5		T25	121		T26	166
valid_sources[0x51]	19502	1			T2	1		T3	1		T37	3
valid_sources[0x52]	22083	1			T37	5		T8	1		T25	144
valid_sources[0x53]	19739	1			T3	2		T37	4		T25	123
valid_sources[0x54]	19491	1			T37	3		T25	138		T26	92
valid_sources[0x55]	18435	1			T7	6		T37	5		T25	133
valid_sources[0x56]	20256	1			T37	2		T25	134		T26	89
valid_sources[0x57]	18914	1			T6	11		T37	3		T50	1
valid_sources[0x58]	21012	1			T6	6		T17	3		T37	6
valid_sources[0x59]	20593	1			T5	2		T7	1		T37	3
valid_sources[0x5a]	20846	1			T37	2		T25	123		T26	254
valid_sources[0x5b]	18952	1			T17	1		T37	3		T25	140
valid_sources[0x5c]	19576	1			T4	1		T6	1		T37	6
valid_sources[0x5d]	17440	1			T3	7		T5	2		T37	1
valid_sources[0x5e]	21365	1			T7	3		T37	2		T25	115
valid_sources[0x5f]	20052	1			T3	4		T4	5		T37	1
valid_sources[0x60]	20290	1			T7	1		T37	8		T25	149
valid_sources[0x61]	20069	1			T6	7		T37	3		T25	132
valid_sources[0x62]	18846	1			T3	2		T17	1		T37	2
valid_sources[0x63]	19781	1			T6	2		T25	146		T26	110
valid_sources[0x64]	20959	1			T37	6		T50	1		T25	121
valid_sources[0x65]	20583	1			T3	1		T37	3		T25	135
valid_sources[0x66]	20151	1			T37	3		T25	130		T26	120
valid_sources[0x67]	19963	1			T19	31		T7	2		T37	3
valid_sources[0x68]	21003	1			T6	11		T37	3		T8	1
valid_sources[0x69]	19413	1			T7	3		T37	2		T25	135
valid_sources[0x6a]	19391	1			T3	1		T5	3		T6	2
valid_sources[0x6b]	22120	1			T21	2		T7	1		T37	3
valid_sources[0x6c]	21557	1			T37	2		T8	1		T25	131
valid_sources[0x6d]	20576	1			T4	2		T6	2		T37	1
valid_sources[0x6e]	19298	1			T6	1		T37	3		T25	140
valid_sources[0x6f]	19449	1			T6	8		T37	2		T25	126
valid_sources[0x70]	21020	1			T3	1		T21	2		T17	2
valid_sources[0x71]	21946	1			T6	7		T37	1		T8	1
valid_sources[0x72]	21310	1			T6	1		T7	3		T37	2
valid_sources[0x73]	19974	1			T6	8		T19	1		T7	1
valid_sources[0x74]	19442	1			T37	3		T8	1		T25	125
valid_sources[0x75]	19685	1			T3	2		T37	4		T8	1
valid_sources[0x76]	20273	1			T17	1		T37	3		T25	136
valid_sources[0x77]	22298	1			T6	5		T37	1		T25	142
valid_sources[0x78]	20243	1			T37	6		T25	133		T27	1055
valid_sources[0x79]	20637	1			T6	19		T37	6		T8	1
valid_sources[0x7a]	20979	1			T4	1		T37	3		T25	148
valid_sources[0x7b]	20063	1			T6	3		T37	1		T8	1
valid_sources[0x7c]	19257	1			T17	1		T37	4		T25	125
valid_sources[0x7d]	19797	1			T6	2		T37	1		T25	135
valid_sources[0x7e]	19603	1			T3	3		T7	1		T37	4
valid_sources[0x7f]	20623	1			T3	2		T7	1		T37	5
valid_sources[0x80]	18770	1			T3	2		T6	8		T25	134

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1153160

1

T1

1

T2

2

T3

2

values[0x0]

all_enables

biggest_size

1712431

1

T1

1

T2

1

T3

12

values[0x1]

all_enables

biggest_size

1712407

1

T1

2

T2

8

T3

6