Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
98.04	98.04	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	98.04	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.04	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	1	39	97.50

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	1	39	97.50	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1362	1			T2	2		T3	1		T6	7
non_zero_bins[1]	924	1			T3	1		T6	2		T20	1
zero	6293	1			T1	3		T2	1		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	2589	1			T2	1		T3	1		T6	9
gen	3022	1			T1	1		T2	1		T3	1
res	46	1			T10	2		T14	2		T68	2
ins	2922	1			T1	2		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6184

1

T1

2

T2

2

T3

2

mubi_true

2395

1

T1

1

T2

1

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

4272

1

T1

2

T2

3

T3

2

pass

4307

1

T1

1

T3

1

T16

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	1	39	97.50	1
Automatically Generated Cross Bins	40	1	39	97.50	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[res]	[zero]	[fail]	[mubi_false]	0	1	1

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	962	1			T2	1		T3	1		T6	2
uni	zero	fail	mubi_true	340	1			T6	1		T19	1		T37	1
uni	zero	pass	mubi_false	957	1			T6	4		T20	1		T37	5
uni	zero	pass	mubi_true	330	1			T6	2		T37	1		T25	10
gen	non_zero_bins[0]	fail	mubi_false	184	1			T2	1		T6	1		T8	1
gen	non_zero_bins[0]	fail	mubi_true	167	1			T6	1		T37	2		T26	2
gen	non_zero_bins[0]	pass	mubi_false	168	1			T6	1		T20	1		T37	2
gen	non_zero_bins[0]	pass	mubi_true	170	1			T26	1		T27	2		T122	3
gen	non_zero_bins[1]	fail	mubi_false	125	1			T25	4		T26	1		T122	2
gen	non_zero_bins[1]	fail	mubi_true	120	1			T3	1		T27	1		T122	2
gen	non_zero_bins[1]	pass	mubi_false	121	1			T10	2		T27	1		T123	2
gen	non_zero_bins[1]	pass	mubi_true	119	1			T26	1		T87	2		T280	4
gen	zero	fail	mubi_false	754	1			T4	1		T6	2		T19	1
gen	zero	fail	mubi_true	152	1			T1	1		T16	1		T6	1
gen	zero	pass	mubi_false	785	1			T6	3		T37	5		T25	10
gen	zero	pass	mubi_true	157	1			T16	1		T21	1		T17	2
res	non_zero_bins[0]	fail	mubi_false	10	1			T14	1		T68	1		T91	1
res	non_zero_bins[0]	fail	mubi_true	2	1			T140	2		-	-		-	-
res	non_zero_bins[0]	pass	mubi_false	8	1			T14	1		T68	1		T91	1
res	non_zero_bins[0]	pass	mubi_true	6	1			T13	2		T281	2		T282	2
res	non_zero_bins[1]	fail	mubi_false	2	1			T283	2		-	-		-	-
res	non_zero_bins[1]	fail	mubi_true	4	1			T11	1		T284	1		T271	1
res	non_zero_bins[1]	pass	mubi_false	5	1			T42	2		T12	2		T285	1
res	non_zero_bins[1]	pass	mubi_true	4	1			T11	1		T284	1		T271	1
res	zero	fail	mubi_true	2	1			T10	1		T96	1		-	-
res	zero	pass	mubi_false	1	1			T285	1		-	-		-	-
res	zero	pass	mubi_true	2	1			T10	1		T96	1		-	-
ins	non_zero_bins[0]	fail	mubi_false	161	1			T6	1		T37	1		T25	3
ins	non_zero_bins[0]	fail	mubi_true	169	1			T2	1		T6	1		T37	1
ins	non_zero_bins[0]	pass	mubi_false	153	1			T3	1		T6	1		T25	2
ins	non_zero_bins[0]	pass	mubi_true	164	1			T6	1		T37	1		T25	1
ins	non_zero_bins[1]	fail	mubi_false	89	1			T6	1		T25	1		T26	1
ins	non_zero_bins[1]	fail	mubi_true	108	1			T20	1		T37	1		T25	4
ins	non_zero_bins[1]	pass	mubi_false	109	1			T37	1		T25	1		T26	1
ins	non_zero_bins[1]	pass	mubi_true	118	1			T6	1		T25	1		T26	1
ins	zero	fail	mubi_false	780	1			T1	1		T4	1		T6	2
ins	zero	fail	mubi_true	141	1			T21	1		T17	1		T26	1
ins	zero	pass	mubi_false	810	1			T1	1		T5	1		T6	1
ins	zero	pass	mubi_true	120	1			T16	1		T21	1		T51	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded