Summary for Variable csrng_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for csrng_glen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
1677 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
glens[1] |
6 |
1 |
|
|
T2 |
1 |
|
T20 |
1 |
|
T91 |
1 |
glens[2] |
4 |
1 |
|
|
T203 |
1 |
|
T90 |
1 |
|
T286 |
1 |
glens[3] |
4 |
1 |
|
|
T287 |
1 |
|
T288 |
1 |
|
T289 |
1 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
1502 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
pass |
1520 |
1 |
|
|
T16 |
1 |
|
T6 |
4 |
|
T20 |
1 |
Summary for Cross csrng_genbits_cross
Samples crossed: csrng_glen csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for csrng_genbits_cross
Bins
csrng_glen | csrng_sts | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
fail |
824 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
glens[0] |
pass |
853 |
1 |
|
|
T16 |
1 |
|
T6 |
2 |
|
T17 |
2 |
glens[1] |
fail |
4 |
1 |
|
|
T2 |
1 |
|
T91 |
1 |
|
T290 |
1 |
glens[1] |
pass |
2 |
1 |
|
|
T20 |
1 |
|
T11 |
1 |
|
- |
- |
glens[2] |
fail |
1 |
1 |
|
|
T269 |
1 |
|
- |
- |
|
- |
- |
glens[2] |
pass |
3 |
1 |
|
|
T203 |
1 |
|
T90 |
1 |
|
T286 |
1 |
glens[3] |
fail |
3 |
1 |
|
|
T287 |
1 |
|
T288 |
1 |
|
T291 |
1 |
glens[3] |
pass |
1 |
1 |
|
|
T289 |
1 |
|
- |
- |
|
- |
- |