SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 14 | 1 | T17 | 2 | T18 | 2 | T109 | 1 | ||||
others[1] | 3 | 1 | T293 | 1 | T294 | 2 | - | - | ||||
others[2] | 11 | 1 | T99 | 1 | T256 | 2 | T257 | 1 | ||||
others[3] | 7 | 1 | T72 | 2 | T295 | 2 | T296 | 2 | ||||
false | 958 | 1 | T1 | 2 | T2 | 1 | T3 | 1 | ||||
true | 177 | 1 | T7 | 3 | T8 | 3 | T10 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2 | 1 | T297 | 1 | T298 | 1 | - | - | ||||
others[1] | 4 | 1 | T254 | 2 | T109 | 1 | T299 | 1 | ||||
others[2] | 5 | 1 | T257 | 1 | T300 | 1 | T293 | 1 | ||||
others[3] | 15 | 1 | T99 | 1 | T253 | 2 | T255 | 2 | ||||
false | 916 | 1 | T2 | 1 | T3 | 1 | T4 | 3 | ||||
true | 228 | 1 | T1 | 2 | T21 | 3 | T50 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8 | 1 | T124 | 1 | T301 | 1 | T257 | 1 | ||||
others[1] | 5 | 1 | T110 | 1 | T302 | 1 | T300 | 1 | ||||
others[2] | 3 | 1 | T33 | 1 | T109 | 1 | T293 | 1 | ||||
others[3] | 9 | 1 | T99 | 1 | T190 | 1 | T89 | 1 | ||||
false | 803 | 1 | T1 | 2 | T2 | 1 | T3 | 1 | ||||
true | 342 | 1 | T4 | 1 | T16 | 2 | T5 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 7 | 1 | T40 | 2 | T109 | 1 | T303 | 2 | ||||
others[1] | 4 | 1 | T200 | 2 | T304 | 2 | - | - | ||||
others[2] | 12 | 1 | T16 | 2 | T305 | 2 | T257 | 1 | ||||
others[3] | 14 | 1 | T99 | 1 | T82 | 2 | T306 | 2 | ||||
false | 375 | 1 | T4 | 1 | T5 | 1 | T21 | 1 | ||||
true | 758 | 1 | T1 | 2 | T2 | 1 | T3 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |