Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	100.00		90.74	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	98.15	100.00	100.00		90.74	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	100.00		90.74	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.15	100.00	100.00		90.74	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T21,T50
1	1	0	1	Covered	T1,T21,T50
1	1	1	0	Covered	T2,T3,T4
1	1	1	1	Covered	T1,T4,T5

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T31,T51
1	1	Covered	T1,T21,T50

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T10,T14,T68
1	1	Covered	T7,T8,T10

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T31,T51

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	49	90.74
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T8,T10,T14
AutoCaptGenCnt	162	Covered	T7,T8,T10
AutoCaptReseedCnt	160	Covered	T8,T10,T14
AutoDispatch	142	Covered	T7,T8,T10
AutoFirstAckWait	135	Covered	T7,T8,T10
AutoLoadIns	90	Covered	T7,T8,T10
AutoSendGenCmd	170	Covered	T7,T8,T10
AutoSendReseedCmd	184	Covered	T10,T14,T68
BootCaptGenCnt	106	Covered	T1,T21,T50
BootDone	126	Covered	T1,T21,T50
BootGenAckWait	116	Covered	T1,T21,T50
BootInsAckWait	102	Covered	T1,T21,T50
BootLoadGen	98	Covered	T1,T21,T50
BootLoadIns	88	Covered	T1,T21,T50
BootPulse	121	Covered	T1,T21,T50
BootSendGenCmd	111	Covered	T1,T21,T50
Error	206	Covered	T4,T5,T21
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T8,T10,T14
AutoAckWait->Error	206	Covered	T57,T135
AutoAckWait->Idle	229	Covered	T10,T14,T68
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T7,T8,T10
AutoCaptGenCnt->Error	206	Covered	T9,T136
AutoCaptGenCnt->Idle	229	Covered	T10,T42,T96
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T10,T14,T68
AutoCaptReseedCnt->Error	206	Covered	T8,T48,T137
AutoCaptReseedCnt->Idle	229	Not Covered
AutoDispatch->AutoCaptGenCnt	162	Covered	T7,T8,T10
AutoDispatch->AutoCaptReseedCnt	160	Covered	T8,T10,T14
AutoDispatch->Error	206	Covered	T132,T138,T139
AutoDispatch->Idle	157	Covered	T91,T11,T140
AutoFirstAckWait->AutoDispatch	142	Covered	T7,T8,T10
AutoFirstAckWait->Error	206	Covered	T129
AutoFirstAckWait->Idle	229	Not Covered
AutoLoadIns->AutoFirstAckWait	135	Covered	T7,T8,T10
AutoLoadIns->Error	206	Covered	T126,T141,T142
AutoLoadIns->Idle	229	Not Covered
AutoSendGenCmd->AutoAckWait	177	Covered	T8,T10,T14
AutoSendGenCmd->Error	206	Covered	T7,T121,T61
AutoSendGenCmd->Idle	229	Covered	T14,T68,T143
AutoSendReseedCmd->AutoAckWait	191	Covered	T10,T14,T68
AutoSendReseedCmd->Error	206	Covered	T144,T145
AutoSendReseedCmd->Idle	229	Not Covered
BootCaptGenCnt->BootSendGenCmd	111	Covered	T1,T21,T50
BootCaptGenCnt->Error	206	Covered	T146,T147,T148
BootCaptGenCnt->Idle	229	Covered	T84,T149,T103
BootDone->Error	206	Covered	T44,T88,T150
BootDone->Idle	229	Covered	T31,T34,T79
BootGenAckWait->BootPulse	121	Covered	T1,T21,T50
BootGenAckWait->Error	206	Covered	T151,T152,T153
BootGenAckWait->Idle	229	Covered	T1,T28,T76
BootInsAckWait->BootCaptGenCnt	106	Covered	T1,T21,T50
BootInsAckWait->Error	206	Covered	T15,T154,T155
BootInsAckWait->Idle	229	Covered	T80,T71,T156
BootLoadGen->BootInsAckWait	102	Covered	T1,T21,T50
BootLoadGen->Error	206	Covered	T50,T157,T158
BootLoadGen->Idle	229	Covered	T51,T29,T159
BootLoadIns->BootLoadGen	98	Covered	T1,T21,T50
BootLoadIns->Error	206	Covered	T160
BootLoadIns->Idle	229	Covered	T73,T78,T161
BootPulse->BootDone	126	Covered	T1,T21,T50
BootPulse->Error	206	Covered	T162,T163
BootPulse->Idle	229	Covered	T67,T75,T164
BootSendGenCmd->BootGenAckWait	116	Covered	T1,T21,T50
BootSendGenCmd->Error	206	Not Covered
BootSendGenCmd->Idle	229	Covered	T77,T165
Idle->AutoLoadIns	90	Covered	T7,T8,T10
Idle->BootLoadIns	88	Covered	T1,T21,T50
Idle->Error	206	Covered	T22,T23,T24
Idle->SWPortMode	93	Covered	T2,T3,T4
SWPortMode->Error	206	Covered	T5,T52,T65
SWPortMode->Idle	229	Covered	T6,T37,T25

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T84,T80,T77
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T21,T50
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T8,T10
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T7,T8,T10
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T8,T10
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T8,T10
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T91,T11,T140
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T7,T8,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T7,T8,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T10,T14,T68
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T14,T68,T91
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T21
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T21,T112

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T21
0	1	Covered	T1,T31,T51
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	188552077	123936	0	0
FpvSecCmErrorStEscalate_A	188552077	124697	0	0
u_state_regs_A	188516367	188390228	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	123936	0	0
T4	575	203	0	0
T5	1096	658	0	0
T6	11106	0	0	0
T7	1706	962	0	0
T8	0	641	0	0
T15	0	446	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	351	0	0
T37	12855	0	0	0
T50	0	430	0	0
T52	0	1110	0	0
T65	0	591	0	0
T66	0	310	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	124697	0	0
T4	575	204	0	0
T5	1096	659	0	0
T6	11106	0	0	0
T7	1706	963	0	0
T8	0	642	0	0
T15	0	447	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	352	0	0
T37	12855	0	0	0
T50	0	431	0	0
T52	0	1111	0	0
T65	0	592	0	0
T66	0	311	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188516367	188390228	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	334	183	0	0
T5	885	731	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	600	483	0	0