EDN Simulation Results

Wednesday September 27 2023 19:02:42 UTC

GitHub Revision: `38769a5e7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2962962794

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.960s	53.372us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.920s	16.012us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	15.141us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.390s	130.741us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.350s	33.627us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.900s	106.612us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	15.141us	20	20	100.00
		edn_csr_aliasing	1.350s	33.627us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.480s	429.605us	50	50	100.00
V2	csrng_commands	edn_genbits	1.480s	429.605us	50	50	100.00
V2	genbits	edn_genbits	1.480s	429.605us	50	50	100.00
V2	interrupts	edn_intr	1.150s	17.790us	50	50	100.00
V2	alerts	edn_alert	1.040s	61.207us	50	50	100.00
V2	errs	edn_err	1.390s	19.248us	100	100	100.00
V2	disable	edn_disable	0.920s	13.710us	47	50	94.00
		edn_disable_auto_req_mode	1.130s	29.031us	11	50	22.00
V2	stress_all	edn_stress_all	4.020s	381.527us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	20.476us	50	50	100.00
V2	alert_test	edn_alert_test	1.040s	43.829us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.050s	679.629us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.050s	679.629us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.920s	16.012us	5	5	100.00
		edn_csr_rw	1.000s	15.141us	20	20	100.00
		edn_csr_aliasing	1.350s	33.627us	5	5	100.00
		edn_same_csr_outstanding	1.310s	34.081us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.920s	16.012us	5	5	100.00
		edn_csr_rw	1.000s	15.141us	20	20	100.00
		edn_csr_aliasing	1.350s	33.627us	5	5	100.00
		edn_same_csr_outstanding	1.310s	34.081us	20	20	100.00
V2		TOTAL			498	540	92.22
V2S	tl_intg_err	edn_sec_cm	7.020s	441.928us	5	5	100.00
		edn_tl_intg_err	6.410s	734.540us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.040s	25.601us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.040s	61.207us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.020s	441.928us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.020s	441.928us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.020s	441.928us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.040s	61.207us	50	50	100.00
		edn_sec_cm	7.020s	441.928us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.040s	61.207us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	6.410s	734.540us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	44.835m	927.945ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			687	730	94.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	9	81.82
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.26	99.02	92.26	96.79	89.47	98.62	99.77	97.91

Failure Buckets

UVM_ERROR (edn_scoreboard.sv:386) scoreboard [scoreboard] Maximum number of request between reseeds in auto_req_mode * exceeded. has 39 failures:

Test edn_disable_auto_req_mode has 39 failures.

0.edn_disable_auto_req_mode.3913748232
Line 213, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

  UVM_ERROR @  11892769 ps: (edn_scoreboard.sv:386) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Maximum number of request between reseeds in auto_req_mode 0x00000000 exceeded.
  UVM_INFO @  11892769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.edn_disable_auto_req_mode.124227928
Line 213, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_disable_auto_req_mode/latest/run.log

  UVM_ERROR @  60651908 ps: (edn_scoreboard.sv:386) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Maximum number of request between reseeds in auto_req_mode 0x00000000 exceeded.
  UVM_INFO @  60651908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 37 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test edn_disable has 2 failures.

31.edn_disable.1235126860
Line 210, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/31.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.edn_disable.3686509526
Line 210, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/44.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (edn_scoreboard.sv:292) scoreboard [scoreboard] Instantiate command not allowed for instantiated CSRNG instance. cmd: * has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 6.edn_stress_all_with_rand_reset.1757318327
    Line 390, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47048348040 ps: (edn_scoreboard.sv:292) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Instantiate command not allowed for instantiated CSRNG instance. cmd: 0x00000901
  UVM_INFO @ 47048348040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

Test edn_disable has 1 failures.

22.edn_disable.470505311
Line 211, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/22.edn_disable/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'h0000ffff) == (exp_vals[4] & 'h0000ffff)))'
  UVM_ERROR @   5453580 ps: (edn_csr_assert_fpv.sv:188) [ASSERT FAILED] ctrl_rd_A
  UVM_INFO @   5453580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---