Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
87.88	87.88	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	87.88	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.88	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	4	17	80.95

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	4	17	80.95	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	61	1			T23	1		T25	1		T31	1
auto_req_mode	67	1			T3	1		T27	1		T26	1
sw_mode	2736	1			T14	3		T15	50		T17	10

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

109

1

T3

1

T23

1

T27

1

single

40

1

T37

1

T24

1

T25

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1242	1			T14	3		T37	1		T23	1
auto[2]	129	1			T253	9		T254	1		T200	6
auto[3]	122	1			T24	1		T114	36		T62	1
auto[4]	55	1			T113	7		T53	1		T55	1
auto[5]	159	1			T8	1		T180	71		T255	2
auto[6]	26	1			T87	1		T256	1		T257	24
auto[7]	1131	1			T3	1		T15	50		T17	10

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	4	17	80.95	4

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[auto_req_mode]	0	1	1
[auto[4] - auto[5]]	[boot_req_mode]	--	--	2
[auto[6]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	52	1			T23	1		T64	1		T34	1
auto[1]	auto_req_mode	57	1			T27	1		T26	1		T7	1
auto[1]	sw_mode	1133	1			T14	3		T37	1		T46	1
auto[2]	boot_req_mode	1	1			T254	1		-	-		-	-
auto[2]	sw_mode	128	1			T253	9		T200	6		T57	1
auto[3]	boot_req_mode	1	1			T258	1		-	-		-	-
auto[3]	auto_req_mode	1	1			T62	1		-	-		-	-
auto[3]	sw_mode	120	1			T24	1		T114	36		T259	80
auto[4]	auto_req_mode	1	1			T53	1		-	-		-	-
auto[4]	sw_mode	54	1			T113	7		T55	1		T260	1
auto[5]	auto_req_mode	1	1			T8	1		-	-		-	-
auto[5]	sw_mode	158	1			T180	71		T255	2		T239	73
auto[6]	boot_req_mode	2	1			T87	1		T256	1		-	-
auto[6]	sw_mode	24	1			T257	24		-	-		-	-
auto[7]	boot_req_mode	5	1			T25	1		T31	1		T77	1
auto[7]	auto_req_mode	7	1			T3	1		T32	1		T78	1
auto[7]	sw_mode	1119	1			T15	50		T17	10		T20	74