Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	0	40	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	0	40	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1566	1			T3	7		T14	2		T15	31
non_zero_bins[1]	1074	1			T3	3		T4	1		T15	19
zero	6801	1			T2	2		T4	1		T12	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	2729	1			T14	3		T15	50		T17	10
gen	3364	1			T2	1		T3	7		T4	1
res	203	1			T3	2		T27	4		T26	3
ins	3145	1			T2	1		T3	1		T4	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6769

1

T2

2

T3

10

T4

1

mubi_true

2672

1

T4

1

T14

2

T15

43

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

4770

1

T3

4

T4

1

T13

2

pass

4671

1

T2

2

T3

6

T4

1

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	0	40	100.00
Automatically Generated Cross Bins	40	0	40	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	1012	1			T14	1		T15	22		T17	2
uni	zero	fail	mubi_true	341	1			T14	1		T15	9		T20	10
uni	zero	pass	mubi_false	1042	1			T14	1		T15	17		T17	6
uni	zero	pass	mubi_true	334	1			T15	2		T17	2		T48	1
gen	non_zero_bins[0]	fail	mubi_false	187	1			T3	3		T14	1		T15	6
gen	non_zero_bins[0]	fail	mubi_true	219	1			T15	2		T27	1		T20	4
gen	non_zero_bins[0]	pass	mubi_false	187	1			T3	4		T15	4		T17	1
gen	non_zero_bins[0]	pass	mubi_true	211	1			T15	2		T17	3		T27	1
gen	non_zero_bins[1]	fail	mubi_false	119	1			T15	2		T5	1		T20	2
gen	non_zero_bins[1]	fail	mubi_true	150	1			T15	3		T17	2		T20	4
gen	non_zero_bins[1]	pass	mubi_false	121	1			T15	2		T20	1		T7	1
gen	non_zero_bins[1]	pass	mubi_true	133	1			T4	1		T15	4		T20	1
gen	zero	fail	mubi_false	906	1			T13	1		T14	2		T15	15
gen	zero	fail	mubi_true	163	1			T15	2		T50	1		T39	1
gen	zero	pass	mubi_false	818	1			T2	1		T12	1		T15	8
gen	zero	pass	mubi_true	150	1			T22	1		T23	2		T9	1
res	non_zero_bins[0]	fail	mubi_false	31	1			T26	2		T8	2		T90	2
res	non_zero_bins[0]	fail	mubi_true	27	1			T7	1		T96	1		T28	1
res	non_zero_bins[0]	pass	mubi_false	24	1			T26	1		T90	1		T269	1
res	non_zero_bins[0]	pass	mubi_true	30	1			T7	1		T96	1		T28	3
res	non_zero_bins[1]	fail	mubi_false	13	1			T3	1		T117	1		T270	2
res	non_zero_bins[1]	fail	mubi_true	19	1			T27	3		T148	3		T84	2
res	non_zero_bins[1]	pass	mubi_false	14	1			T3	1		T117	2		T270	1
res	non_zero_bins[1]	pass	mubi_true	14	1			T27	1		T84	1		T58	3
res	zero	fail	mubi_false	10	1			T271	2		T272	1		T273	4
res	zero	fail	mubi_true	7	1			T274	1		T275	1		T78	1
res	zero	pass	mubi_false	11	1			T111	2		T274	1		T275	1
res	zero	pass	mubi_true	3	1			T78	1		T152	1		T241	1
ins	non_zero_bins[0]	fail	mubi_false	162	1			T15	1		T20	4		T26	1
ins	non_zero_bins[0]	fail	mubi_true	165	1			T15	7		T17	2		T27	1
ins	non_zero_bins[0]	pass	mubi_false	154	1			T15	3		T17	1		T24	1
ins	non_zero_bins[0]	pass	mubi_true	169	1			T14	1		T15	6		T17	1
ins	non_zero_bins[1]	fail	mubi_false	115	1			T15	1		T20	2		T21	3
ins	non_zero_bins[1]	fail	mubi_true	125	1			T15	2		T17	1		T20	6
ins	non_zero_bins[1]	pass	mubi_false	108	1			T3	1		T15	2		T17	1
ins	non_zero_bins[1]	pass	mubi_true	143	1			T15	3		T20	1		T7	1
ins	zero	fail	mubi_false	866	1			T4	1		T13	1		T14	2
ins	zero	fail	mubi_true	133	1			T15	1		T17	1		T50	1
ins	zero	pass	mubi_false	869	1			T2	1		T12	1		T15	9
ins	zero	pass	mubi_true	136	1			T20	3		T10	1		T52	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded