Summary for Variable csrng_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for csrng_glen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
1984 |
1 |
|
|
T2 |
1 |
|
T3 |
7 |
|
T4 |
1 |
glens[1] |
6 |
1 |
|
|
T37 |
1 |
|
T24 |
1 |
|
T7 |
1 |
glens[2] |
4 |
1 |
|
|
T190 |
1 |
|
T254 |
1 |
|
T265 |
1 |
glens[3] |
1 |
1 |
|
|
T52 |
1 |
|
- |
- |
|
- |
- |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
1744 |
1 |
|
|
T3 |
3 |
|
T13 |
1 |
|
T14 |
3 |
pass |
1620 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T4 |
1 |
Summary for Cross csrng_genbits_cross
Samples crossed: csrng_glen csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
1 |
7 |
87.50 |
1 |
Automatically Generated Cross Bins for csrng_genbits_cross
Uncovered bins
csrng_glen | csrng_sts | COUNT | AT LEAST | NUMBER | STATUS |
[glens[3]] |
[fail] |
0 |
1 |
1 |
|
Covered bins
csrng_glen | csrng_sts | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
fail |
1029 |
1 |
|
|
T3 |
3 |
|
T13 |
1 |
|
T14 |
2 |
glens[0] |
pass |
955 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T4 |
1 |
glens[1] |
fail |
3 |
1 |
|
|
T32 |
1 |
|
T266 |
1 |
|
T267 |
1 |
glens[1] |
pass |
3 |
1 |
|
|
T37 |
1 |
|
T24 |
1 |
|
T7 |
1 |
glens[2] |
fail |
2 |
1 |
|
|
T190 |
1 |
|
T268 |
1 |
|
- |
- |
glens[2] |
pass |
2 |
1 |
|
|
T254 |
1 |
|
T265 |
1 |
|
- |
- |
glens[3] |
pass |
1 |
1 |
|
|
T52 |
1 |
|
- |
- |
|
- |
- |