SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8 | 1 | T98 | 1 | T277 | 1 | T65 | 2 | ||||
others[1] | 16 | 1 | T61 | 1 | T242 | 2 | T246 | 2 | ||||
others[2] | 7 | 1 | T119 | 1 | T278 | 2 | T279 | 2 | ||||
others[3] | 17 | 1 | T80 | 2 | T280 | 1 | T281 | 2 | ||||
false | 1031 | 1 | T2 | 3 | T3 | 3 | T4 | 4 | ||||
true | 366 | 1 | T3 | 1 | T4 | 3 | T5 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T282 | 2 | T283 | 2 | - | - | ||||
others[1] | 4 | 1 | T277 | 1 | T284 | 1 | T285 | 2 | ||||
others[2] | 6 | 1 | T286 | 1 | T287 | 1 | T73 | 2 | ||||
others[3] | 16 | 1 | T61 | 1 | T98 | 1 | T119 | 1 | ||||
false | 1185 | 1 | T2 | 3 | T3 | 4 | T4 | 7 | ||||
true | 230 | 1 | T50 | 3 | T22 | 3 | T23 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8 | 1 | T9 | 1 | T119 | 1 | T286 | 1 | ||||
others[1] | 4 | 1 | T61 | 1 | T288 | 1 | T289 | 1 | ||||
others[2] | 5 | 1 | T247 | 1 | T248 | 1 | T290 | 1 | ||||
others[3] | 3 | 1 | T287 | 1 | T291 | 1 | T292 | 1 | ||||
false | 1004 | 1 | T2 | 2 | T3 | 3 | T4 | 4 | ||||
true | 421 | 1 | T2 | 1 | T3 | 1 | T4 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 1 | 1 | T284 | 1 | - | - | - | - | ||||
others[1] | 5 | 1 | T61 | 1 | T293 | 2 | T294 | 2 | ||||
others[2] | 10 | 1 | T10 | 2 | T98 | 1 | T243 | 2 | ||||
others[3] | 7 | 1 | T11 | 2 | T119 | 1 | T277 | 1 | ||||
false | 567 | 1 | T2 | 1 | T3 | 2 | T4 | 5 | ||||
true | 855 | 1 | T2 | 2 | T3 | 2 | T4 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |