Line Coverage for Module :
edn_ack_sm
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
edn_ack_sm
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Module :
edn_ack_sm
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T12,T13,T14 |
DataWait |
75 |
Covered |
T4,T12,T13 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Covered |
T91,T172 |
AckPls->Error |
99 |
Covered |
T12,T6,T227 |
AckPls->Idle |
85 |
Covered |
T13,T14,T15 |
DataWait->AckPls |
80 |
Covered |
T12,T13,T14 |
DataWait->Disabled |
107 |
Covered |
T28,T34,T54 |
DataWait->Error |
99 |
Covered |
T4,T50,T22 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T4,T12,T13 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T12 |
Branch Coverage for Module :
edn_ack_sm
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T13,T14,T15 |
Idle |
- |
1 |
0 |
- |
Covered |
T4,T12,T13 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T12,T13,T14 |
DataWait |
- |
- |
- |
0 |
Covered |
T4,T12,T14 |
AckPls |
- |
- |
- |
- |
Covered |
T12,T13,T14 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T5,T22 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
edn_ack_sm
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1447663434 |
914139 |
0 |
0 |
T1 |
109683 |
31990 |
0 |
0 |
T2 |
5117 |
2436 |
0 |
0 |
T3 |
12670 |
0 |
0 |
0 |
T4 |
8519 |
2856 |
0 |
0 |
T5 |
0 |
2470 |
0 |
0 |
T6 |
0 |
1554 |
0 |
0 |
T12 |
4368 |
1785 |
0 |
0 |
T13 |
13741 |
0 |
0 |
0 |
T14 |
36498 |
0 |
0 |
0 |
T15 |
2246580 |
0 |
0 |
0 |
T16 |
11298 |
0 |
0 |
0 |
T17 |
78211 |
0 |
0 |
0 |
T22 |
0 |
7748 |
0 |
0 |
T39 |
0 |
4284 |
0 |
0 |
T40 |
0 |
2590 |
0 |
0 |
T50 |
0 |
1960 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1447663434 |
920110 |
0 |
0 |
T1 |
109683 |
32620 |
0 |
0 |
T2 |
5117 |
2443 |
0 |
0 |
T3 |
12670 |
0 |
0 |
0 |
T4 |
8519 |
2863 |
0 |
0 |
T5 |
0 |
2477 |
0 |
0 |
T6 |
0 |
1561 |
0 |
0 |
T12 |
4368 |
1792 |
0 |
0 |
T13 |
13741 |
0 |
0 |
0 |
T14 |
36498 |
0 |
0 |
0 |
T15 |
2246580 |
0 |
0 |
0 |
T16 |
11298 |
0 |
0 |
0 |
T17 |
78211 |
0 |
0 |
0 |
T22 |
0 |
7755 |
0 |
0 |
T39 |
0 |
4291 |
0 |
0 |
T40 |
0 |
2597 |
0 |
0 |
T50 |
0 |
1967 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1447624693 |
1446698824 |
0 |
0 |
T1 |
109683 |
57008 |
0 |
0 |
T2 |
5005 |
4172 |
0 |
0 |
T3 |
12670 |
12082 |
0 |
0 |
T4 |
8301 |
7335 |
0 |
0 |
T12 |
4144 |
2961 |
0 |
0 |
T13 |
13673 |
12343 |
0 |
0 |
T14 |
36498 |
35021 |
0 |
0 |
T15 |
2246580 |
2246496 |
0 |
0 |
T16 |
11298 |
10836 |
0 |
0 |
T17 |
78211 |
73752 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
12 |
85.71 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T2,T26,T25 |
DataWait |
75 |
Covered |
T2,T26,T25 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Not Covered |
|
AckPls->Error |
99 |
Not Covered |
|
AckPls->Idle |
85 |
Covered |
T2,T26,T25 |
DataWait->AckPls |
80 |
Covered |
T2,T26,T25 |
DataWait->Disabled |
107 |
Covered |
T71,T92,T133 |
DataWait->Error |
99 |
Covered |
T164,T150,T173 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T2,T26,T25 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T12 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T2,T26,T25 |
Idle |
- |
1 |
0 |
- |
Covered |
T2,T26,T25 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T2,T26,T25 |
DataWait |
- |
- |
- |
0 |
Covered |
T26,T25,T8 |
AckPls |
- |
- |
- |
- |
Covered |
T2,T26,T25 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
130927 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
360 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1114 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
131780 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
361 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1115 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
12 |
85.71 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T3,T9,T10 |
DataWait |
75 |
Covered |
T3,T9,T10 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Not Covered |
|
AckPls->Error |
99 |
Not Covered |
|
AckPls->Idle |
85 |
Covered |
T3,T9,T10 |
DataWait->AckPls |
80 |
Covered |
T3,T9,T10 |
DataWait->Disabled |
107 |
Covered |
T82,T228,T229 |
DataWait->Error |
99 |
Covered |
T43,T230,T231 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T3,T9,T10 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T12 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T3,T9,T10 |
Idle |
- |
1 |
0 |
- |
Covered |
T3,T9,T10 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T3,T9,T10 |
DataWait |
- |
- |
- |
0 |
Covered |
T3,T9,T10 |
AckPls |
- |
- |
- |
- |
Covered |
T3,T9,T10 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
130927 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
360 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1114 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
131780 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
361 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1115 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
12 |
85.71 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T27,T25,T28 |
DataWait |
75 |
Covered |
T27,T25,T28 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Not Covered |
|
AckPls->Error |
99 |
Not Covered |
|
AckPls->Idle |
85 |
Covered |
T27,T25,T28 |
DataWait->AckPls |
80 |
Covered |
T27,T25,T28 |
DataWait->Disabled |
107 |
Covered |
T34,T85,T88 |
DataWait->Error |
99 |
Covered |
T161,T232,T163 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T27,T25,T28 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T12 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T27,T25,T28 |
Idle |
- |
1 |
0 |
- |
Covered |
T27,T25,T28 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T27,T25,T28 |
DataWait |
- |
- |
- |
0 |
Covered |
T27,T25,T28 |
AckPls |
- |
- |
- |
- |
Covered |
T27,T25,T28 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
130927 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
360 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1114 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
131780 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
361 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1115 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
13 |
92.86 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T23,T29,T25 |
DataWait |
75 |
Covered |
T4,T22,T23 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Not Covered |
|
AckPls->Error |
99 |
Covered |
T227 |
AckPls->Idle |
85 |
Covered |
T23,T29,T25 |
DataWait->AckPls |
80 |
Covered |
T23,T29,T25 |
DataWait->Disabled |
107 |
Covered |
T54,T233 |
DataWait->Error |
99 |
Covered |
T4,T22,T39 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T4,T22,T23 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T12,T50 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T23,T29,T25 |
Idle |
- |
1 |
0 |
- |
Covered |
T4,T22,T23 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T23,T29,T25 |
DataWait |
- |
- |
- |
0 |
Covered |
T4,T22,T23 |
AckPls |
- |
- |
- |
- |
Covered |
T23,T29,T25 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
130927 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
360 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1114 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
131780 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
361 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1115 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
13 |
92.86 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T12,T24,T25 |
DataWait |
75 |
Covered |
T12,T24,T25 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Not Covered |
|
AckPls->Error |
99 |
Covered |
T12 |
AckPls->Idle |
85 |
Covered |
T24,T25,T8 |
DataWait->AckPls |
80 |
Covered |
T12,T24,T25 |
DataWait->Disabled |
107 |
Covered |
T28,T67,T234 |
DataWait->Error |
99 |
Covered |
T143 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T12,T24,T25 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T50 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T24,T25,T8 |
Idle |
- |
1 |
0 |
- |
Covered |
T12,T24,T25 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T12,T24,T25 |
DataWait |
- |
- |
- |
0 |
Covered |
T12,T24,T25 |
AckPls |
- |
- |
- |
- |
Covered |
T12,T24,T25 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
130927 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
360 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1114 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
131780 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
361 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1115 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T13,T14,T15 |
DataWait |
75 |
Covered |
T13,T14,T15 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Covered |
T172 |
AckPls->Error |
99 |
Covered |
T235,T236,T237 |
AckPls->Idle |
85 |
Covered |
T13,T14,T15 |
DataWait->AckPls |
80 |
Covered |
T13,T14,T15 |
DataWait->Disabled |
107 |
Covered |
T238,T239,T121 |
DataWait->Error |
99 |
Covered |
T50,T40,T42 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T18,T240 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T13,T14,T15 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T12 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T13,T14,T15 |
Idle |
- |
1 |
0 |
- |
Covered |
T13,T14,T15 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T13,T14,T15 |
DataWait |
- |
- |
- |
0 |
Covered |
T14,T15,T17 |
AckPls |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T5,T22 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
128577 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
310 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1064 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
129430 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
311 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1065 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206770321 |
206638054 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
619 |
500 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
999 |
861 |
0 |
0 |
T12 |
400 |
231 |
0 |
0 |
T13 |
1895 |
1705 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 32 | 32 | 100.00 |
ALWAYS | 52 | 3 | 3 | 100.00 |
ALWAYS | 55 | 29 | 29 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
52 |
3 |
3 |
55 |
1 |
1 |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
60 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
|
|
|
MISSING_ELSE |
68 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
75 |
1 |
1 |
|
|
|
MISSING_ELSE |
79 |
1 |
1 |
80 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
88 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
| Total | Covered | Percent |
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 104
EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
------1------ ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T13,T23,T27 |
FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
6 |
6 |
100.00 |
(Not included in score) |
Transitions |
14 |
14 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
AckPls |
80 |
Covered |
T5,T6,T25 |
DataWait |
75 |
Covered |
T5,T6,T25 |
Disabled |
107 |
Covered |
T1,T2,T3 |
EndPointClear |
63 |
Covered |
T1,T2,T3 |
Error |
99 |
Covered |
T1,T2,T4 |
Idle |
68 |
Covered |
T1,T2,T3 |
transitions | Line No. | Covered | Tests |
AckPls->Disabled |
107 |
Covered |
T91 |
AckPls->Error |
99 |
Covered |
T6 |
AckPls->Idle |
85 |
Covered |
T5,T25,T90 |
DataWait->AckPls |
80 |
Covered |
T5,T6,T25 |
DataWait->Disabled |
107 |
Covered |
T36,T93,T241 |
DataWait->Error |
99 |
Covered |
T140 |
Disabled->EndPointClear |
63 |
Covered |
T1,T2,T3 |
Disabled->Error |
99 |
Covered |
T1,T18,T19 |
EndPointClear->Disabled |
107 |
Covered |
T26,T64,T90 |
EndPointClear->Error |
99 |
Covered |
T1,T75,T18 |
EndPointClear->Idle |
68 |
Covered |
T1,T2,T3 |
Idle->DataWait |
75 |
Covered |
T5,T6,T25 |
Idle->Disabled |
107 |
Covered |
T1,T13,T14 |
Idle->Error |
99 |
Covered |
T2,T4,T12 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
| Line No. | Total | Covered | Percent |
Branches |
|
16 |
16 |
100.00 |
IF |
52 |
2 |
2 |
100.00 |
CASE |
60 |
11 |
11 |
100.00 |
IF |
98 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 52 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 60 case (state_q)
-2-: 62 if (enable_i)
-3-: 71 if (req_i)
-4-: 72 if (fifo_not_empty_i)
-5-: 79 if (fifo_not_empty_i)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
Disabled |
1 |
- |
- |
- |
Covered |
T1,T2,T3 |
Disabled |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
EndPointClear |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
Idle |
- |
1 |
1 |
- |
Covered |
T5,T25,T90 |
Idle |
- |
1 |
0 |
- |
Covered |
T5,T6,T25 |
Idle |
- |
0 |
- |
- |
Covered |
T1,T2,T3 |
DataWait |
- |
- |
- |
1 |
Covered |
T5,T6,T25 |
DataWait |
- |
- |
- |
0 |
Covered |
T5,T6,T25 |
AckPls |
- |
- |
- |
- |
Covered |
T5,T6,T25 |
Error |
- |
- |
- |
- |
Covered |
T1,T2,T4 |
default |
- |
- |
- |
- |
Covered |
T1,T18,T19 |
LineNo. Expression
-1-: 98 if (local_escalate_i)
-2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T4 |
0 |
1 |
Covered |
T13,T23,T27 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Assertion Details
AckSmErrorStStable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
130927 |
0 |
0 |
T1 |
15669 |
4570 |
0 |
0 |
T2 |
731 |
348 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
408 |
0 |
0 |
T5 |
0 |
360 |
0 |
0 |
T6 |
0 |
222 |
0 |
0 |
T12 |
624 |
255 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1114 |
0 |
0 |
T39 |
0 |
612 |
0 |
0 |
T40 |
0 |
370 |
0 |
0 |
T50 |
0 |
280 |
0 |
0 |
FpvSecCmErrorStEscalate_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
131780 |
0 |
0 |
T1 |
15669 |
4660 |
0 |
0 |
T2 |
731 |
349 |
0 |
0 |
T3 |
1810 |
0 |
0 |
0 |
T4 |
1217 |
409 |
0 |
0 |
T5 |
0 |
361 |
0 |
0 |
T6 |
0 |
223 |
0 |
0 |
T12 |
624 |
256 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
1115 |
0 |
0 |
T39 |
0 |
613 |
0 |
0 |
T40 |
0 |
371 |
0 |
0 |
T50 |
0 |
281 |
0 |
0 |
u_state_regs_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |