Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 26 | 23 | 88.46 |
Logical | 26 | 23 | 88.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T13 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T3,T4,T15 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T3,T4,T15 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T27,T26 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T105,T102,T103 |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T13 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T13 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T3,T4,T13 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T3,T4,T15 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620075112 |
247841 |
0 |
0 |
T2 |
731 |
2 |
0 |
0 |
T3 |
5430 |
1308 |
0 |
0 |
T4 |
1789 |
215 |
0 |
0 |
T5 |
374 |
117 |
0 |
0 |
T6 |
0 |
63 |
0 |
0 |
T7 |
0 |
901 |
0 |
0 |
T8 |
0 |
551 |
0 |
0 |
T12 |
814 |
3 |
0 |
0 |
T13 |
2581 |
3 |
0 |
0 |
T14 |
15642 |
23 |
0 |
0 |
T15 |
962820 |
609 |
0 |
0 |
T16 |
4842 |
0 |
0 |
0 |
T17 |
33519 |
153 |
0 |
0 |
T22 |
0 |
7 |
0 |
0 |
T23 |
0 |
46 |
0 |
0 |
T26 |
0 |
3909 |
0 |
0 |
T27 |
0 |
3242 |
0 |
0 |
T28 |
0 |
1614 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T50 |
1702 |
5 |
0 |
0 |
T96 |
0 |
537 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620427186 |
620030385 |
0 |
0 |
T1 |
47007 |
24432 |
0 |
0 |
T2 |
2193 |
1836 |
0 |
0 |
T3 |
5430 |
5178 |
0 |
0 |
T4 |
3651 |
3237 |
0 |
0 |
T12 |
1872 |
1365 |
0 |
0 |
T13 |
5889 |
5319 |
0 |
0 |
T14 |
15642 |
15009 |
0 |
0 |
T15 |
962820 |
962784 |
0 |
0 |
T16 |
4842 |
4644 |
0 |
0 |
T17 |
33519 |
31608 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620427186 |
620030385 |
0 |
0 |
T1 |
47007 |
24432 |
0 |
0 |
T2 |
2193 |
1836 |
0 |
0 |
T3 |
5430 |
5178 |
0 |
0 |
T4 |
3651 |
3237 |
0 |
0 |
T12 |
1872 |
1365 |
0 |
0 |
T13 |
5889 |
5319 |
0 |
0 |
T14 |
15642 |
15009 |
0 |
0 |
T15 |
962820 |
962784 |
0 |
0 |
T16 |
4842 |
4644 |
0 |
0 |
T17 |
33519 |
31608 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620427186 |
620030385 |
0 |
0 |
T1 |
47007 |
24432 |
0 |
0 |
T2 |
2193 |
1836 |
0 |
0 |
T3 |
5430 |
5178 |
0 |
0 |
T4 |
3651 |
3237 |
0 |
0 |
T12 |
1872 |
1365 |
0 |
0 |
T13 |
5889 |
5319 |
0 |
0 |
T14 |
15642 |
15009 |
0 |
0 |
T15 |
962820 |
962784 |
0 |
0 |
T16 |
4842 |
4644 |
0 |
0 |
T17 |
33519 |
31608 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
620427186 |
296482 |
0 |
0 |
T2 |
731 |
2 |
0 |
0 |
T3 |
5430 |
1308 |
0 |
0 |
T4 |
3651 |
1083 |
0 |
0 |
T5 |
1810 |
800 |
0 |
0 |
T6 |
0 |
528 |
0 |
0 |
T7 |
0 |
442 |
0 |
0 |
T8 |
0 |
551 |
0 |
0 |
T12 |
1872 |
3 |
0 |
0 |
T13 |
5889 |
33 |
0 |
0 |
T14 |
15642 |
23 |
0 |
0 |
T15 |
962820 |
609 |
0 |
0 |
T16 |
4842 |
0 |
0 |
0 |
T17 |
33519 |
153 |
0 |
0 |
T22 |
0 |
19 |
0 |
0 |
T23 |
0 |
46 |
0 |
0 |
T26 |
0 |
1949 |
0 |
0 |
T27 |
0 |
3242 |
0 |
0 |
T39 |
0 |
46 |
0 |
0 |
T40 |
0 |
46 |
0 |
0 |
T50 |
4662 |
51 |
0 |
0 |
T96 |
0 |
537 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
| Total | Covered | Percent |
Conditions | 26 | 18 | 69.23 |
Logical | 26 | 18 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T3,T15,T17 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T3,T15,T17 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T2,T3,T4 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T2,T3,T4 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T3,T4 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T2,T3,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
88 |
3 |
2 |
66.67 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T3,T15,T17 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T4 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T4 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
36176 |
0 |
0 |
T2 |
731 |
2 |
0 |
0 |
T3 |
1810 |
108 |
0 |
0 |
T4 |
1217 |
16 |
0 |
0 |
T5 |
0 |
18 |
0 |
0 |
T12 |
624 |
3 |
0 |
0 |
T13 |
1963 |
3 |
0 |
0 |
T14 |
5214 |
23 |
0 |
0 |
T15 |
320940 |
609 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
153 |
0 |
0 |
T50 |
1554 |
5 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
36176 |
0 |
0 |
T2 |
731 |
2 |
0 |
0 |
T3 |
1810 |
108 |
0 |
0 |
T4 |
1217 |
16 |
0 |
0 |
T5 |
0 |
18 |
0 |
0 |
T12 |
624 |
3 |
0 |
0 |
T13 |
1963 |
3 |
0 |
0 |
T14 |
5214 |
23 |
0 |
0 |
T15 |
320940 |
609 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
153 |
0 |
0 |
T50 |
1554 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Total | Covered | Percent |
Conditions | 26 | 23 | 88.46 |
Logical | 26 | 23 | 88.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T6,T30 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T3,T27,T26 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T3,T27,T26 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T13,T30,T101 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T13 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T105,T106,T107 |
1 | 0 | 1 | Covered | T3,T4,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T27,T26 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T13,T6,T30 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T13 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T6,T30 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T13 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T13,T6,T30 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T3,T27,T26 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T13 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T13 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206633025 |
102099 |
0 |
0 |
T3 |
1810 |
595 |
0 |
0 |
T4 |
286 |
63 |
0 |
0 |
T5 |
187 |
47 |
0 |
0 |
T6 |
0 |
29 |
0 |
0 |
T7 |
0 |
442 |
0 |
0 |
T8 |
0 |
551 |
0 |
0 |
T12 |
95 |
0 |
0 |
0 |
T13 |
309 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T26 |
0 |
1949 |
0 |
0 |
T27 |
0 |
1280 |
0 |
0 |
T28 |
0 |
1614 |
0 |
0 |
T50 |
74 |
0 |
0 |
0 |
T96 |
0 |
537 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
124231 |
0 |
0 |
T3 |
1810 |
595 |
0 |
0 |
T4 |
1217 |
474 |
0 |
0 |
T5 |
905 |
378 |
0 |
0 |
T6 |
0 |
261 |
0 |
0 |
T7 |
0 |
442 |
0 |
0 |
T8 |
0 |
551 |
0 |
0 |
T12 |
624 |
0 |
0 |
0 |
T13 |
1963 |
30 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T26 |
0 |
1949 |
0 |
0 |
T27 |
0 |
1280 |
0 |
0 |
T50 |
1554 |
0 |
0 |
0 |
T96 |
0 |
537 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Total | Covered | Percent |
Conditions | 26 | 23 | 88.46 |
Logical | 26 | 23 | 88.46 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T27,T26,T74 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T50 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T102,T103,T104 |
1 | 0 | 1 | Covered | T3,T4,T50 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T50 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T50 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T50 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T3,T4,T5 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T3,T4,T5 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T50 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T50 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206633025 |
109566 |
0 |
0 |
T3 |
1810 |
605 |
0 |
0 |
T4 |
286 |
136 |
0 |
0 |
T5 |
187 |
52 |
0 |
0 |
T6 |
0 |
34 |
0 |
0 |
T7 |
0 |
459 |
0 |
0 |
T12 |
95 |
0 |
0 |
0 |
T13 |
309 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
7 |
0 |
0 |
T23 |
0 |
46 |
0 |
0 |
T26 |
0 |
1960 |
0 |
0 |
T27 |
0 |
1962 |
0 |
0 |
T40 |
0 |
4 |
0 |
0 |
T50 |
74 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
206676795 |
0 |
0 |
T1 |
15669 |
8144 |
0 |
0 |
T2 |
731 |
612 |
0 |
0 |
T3 |
1810 |
1726 |
0 |
0 |
T4 |
1217 |
1079 |
0 |
0 |
T12 |
624 |
455 |
0 |
0 |
T13 |
1963 |
1773 |
0 |
0 |
T14 |
5214 |
5003 |
0 |
0 |
T15 |
320940 |
320928 |
0 |
0 |
T16 |
1614 |
1548 |
0 |
0 |
T17 |
11173 |
10536 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
206809062 |
136075 |
0 |
0 |
T3 |
1810 |
605 |
0 |
0 |
T4 |
1217 |
593 |
0 |
0 |
T5 |
905 |
404 |
0 |
0 |
T6 |
0 |
267 |
0 |
0 |
T12 |
624 |
0 |
0 |
0 |
T13 |
1963 |
0 |
0 |
0 |
T14 |
5214 |
0 |
0 |
0 |
T15 |
320940 |
0 |
0 |
0 |
T16 |
1614 |
0 |
0 |
0 |
T17 |
11173 |
0 |
0 |
0 |
T22 |
0 |
19 |
0 |
0 |
T23 |
0 |
46 |
0 |
0 |
T27 |
0 |
1962 |
0 |
0 |
T39 |
0 |
46 |
0 |
0 |
T40 |
0 |
46 |
0 |
0 |
T50 |
1554 |
46 |
0 |
0 |