Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
72.73	72.73	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	72.73	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.73	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	9	12	57.14

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	9	12	57.14	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	63	1			T24	1		T59	1		T38	1
auto_req_mode	59	1			T8	1		T9	1		T13	1
sw_mode	2974	1			T2	1		T32	1		T33	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

108

1

T9

1

T13

1

T32

1

single

41

1

T8

1

T28

1

T30

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1242	1			T2	1		T8	1		T9	1
auto[2]	38	1			T20	26		T64	1		T65	1
auto[3]	65	1			T44	4		T117	6		T273	47
auto[4]	77	1			T274	24		T275	48		T276	5
auto[5]	202	1			T23	1		T22	74		T277	55
auto[6]	135	1			T183	26		T185	69		T278	7
auto[7]	1337	1			T43	15		T35	1		T24	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	9	12	57.14	9

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[auto_req_mode]	0	1	1
[auto[3] - auto[6]]	[boot_req_mode , auto_req_mode]	--	--	8

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	53	1			T59	1		T38	1		T60	1
auto[1]	auto_req_mode	57	1			T8	1		T9	1		T13	1
auto[1]	sw_mode	1132	1			T2	1		T32	1		T33	1
auto[2]	boot_req_mode	2	1			T64	1		T279	1		-	-
auto[2]	sw_mode	36	1			T20	26		T65	1		T280	9
auto[3]	sw_mode	65	1			T44	4		T117	6		T273	47
auto[4]	sw_mode	77	1			T274	24		T275	48		T276	5
auto[5]	sw_mode	202	1			T23	1		T22	74		T277	55
auto[6]	sw_mode	135	1			T183	26		T185	69		T278	7
auto[7]	boot_req_mode	8	1			T24	1		T79	1		T281	1
auto[7]	auto_req_mode	2	1			T10	1		T12	1		-	-
auto[7]	sw_mode	1327	1			T43	15		T35	1		T29	1