Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	667459	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6078228

1

T1

97

T2

8

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1740430	1			T1	251		T2	25		T3	54
values[0x0]	2320063	1			T1	11		T2	8		T3	6
values[0x1]	2685194	1			T1	7		T2	1		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	318558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6427129

1

T1

142

T2

13

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28246	1			T5	1		T43	5		T44	1
valid_sources[0x01]	25641	1			T9	1		T14	1		T43	16
valid_sources[0x02]	26159	1			T5	1		T9	1		T14	1
valid_sources[0x03]	27621	1			T43	3		T58	1		T20	141
valid_sources[0x04]	28286	1			T14	1		T26	1		T44	2
valid_sources[0x05]	25668	1			T2	1		T5	1		T9	1
valid_sources[0x06]	25153	1			T43	1		T23	5		T44	1
valid_sources[0x07]	26377	1			T5	1		T14	1		T34	1
valid_sources[0x08]	26215	1			T44	3		T58	1		T45	1
valid_sources[0x09]	26267	1			T9	2		T56	5		T44	4
valid_sources[0x0a]	25035	1			T32	1		T44	4		T45	3
valid_sources[0x0b]	26078	1			T13	3		T43	2		T23	6
valid_sources[0x0c]	26632	1			T5	2		T9	2		T43	1
valid_sources[0x0d]	26785	1			T43	4		T45	2		T20	172
valid_sources[0x0e]	25885	1			T1	5		T56	1		T44	3
valid_sources[0x0f]	27059	1			T9	1		T14	1		T32	3
valid_sources[0x10]	27868	1			T5	1		T43	9		T24	1
valid_sources[0x11]	25914	1			T5	3		T26	1		T44	2
valid_sources[0x12]	26419	1			T9	1		T14	2		T32	1
valid_sources[0x13]	26754	1			T5	1		T9	1		T34	1
valid_sources[0x14]	25439	1			T26	1		T43	2		T20	102
valid_sources[0x15]	27759	1			T14	1		T13	11		T44	1
valid_sources[0x16]	25636	1			T9	1		T14	2		T25	1
valid_sources[0x17]	25753	1			T5	1		T16	2		T33	4
valid_sources[0x18]	26744	1			T44	1		T29	2		T7	5
valid_sources[0x19]	26262	1			T16	1		T46	7		T56	1
valid_sources[0x1a]	25917	1			T9	1		T32	1		T25	1
valid_sources[0x1b]	24903	1			T5	2		T25	1		T34	1
valid_sources[0x1c]	25070	1			T14	1		T32	1		T34	1
valid_sources[0x1d]	26061	1			T34	1		T43	2		T44	2
valid_sources[0x1e]	27491	1			T1	10		T4	55		T14	1
valid_sources[0x1f]	26186	1			T2	1		T9	1		T28	5
valid_sources[0x20]	28616	1			T2	2		T43	7		T44	1
valid_sources[0x21]	26752	1			T25	1		T34	1		T43	10
valid_sources[0x22]	26385	1			T9	1		T46	2		T43	8
valid_sources[0x23]	26199	1			T2	1		T5	2		T32	3
valid_sources[0x24]	26516	1			T32	1		T46	1		T43	2
valid_sources[0x25]	26789	1			T25	1		T58	1		T20	148
valid_sources[0x26]	26778	1			T2	1		T43	1		T45	4
valid_sources[0x27]	27117	1			T14	2		T57	4		T23	10
valid_sources[0x28]	26445	1			T5	2		T9	1		T14	1
valid_sources[0x29]	26449	1			T26	1		T44	1		T20	146
valid_sources[0x2a]	26406	1			T25	2		T44	1		T35	1
valid_sources[0x2b]	25767	1			T34	1		T44	2		T35	1
valid_sources[0x2c]	27647	1			T9	1		T34	1		T43	7
valid_sources[0x2d]	25569	1			T14	3		T43	5		T44	2
valid_sources[0x2e]	27672	1			T1	6		T9	1		T33	4
valid_sources[0x2f]	25392	1			T32	1		T25	1		T26	1
valid_sources[0x30]	27121	1			T2	2		T9	1		T14	1
valid_sources[0x31]	24726	1			T5	1		T9	1		T43	4
valid_sources[0x32]	26916	1			T6	108		T43	2		T23	2
valid_sources[0x33]	26257	1			T9	1		T32	1		T25	1
valid_sources[0x34]	24773	1			T5	1		T9	2		T44	1
valid_sources[0x35]	26546	1			T26	1		T43	4		T44	3
valid_sources[0x36]	26136	1			T32	2		T44	1		T20	146
valid_sources[0x37]	25852	1			T5	4		T16	2		T43	4
valid_sources[0x38]	26756	1			T9	1		T23	9		T29	3
valid_sources[0x39]	25287	1			T26	1		T43	9		T44	1
valid_sources[0x3a]	27197	1			T32	1		T43	5		T45	2
valid_sources[0x3b]	25494	1			T5	2		T9	1		T14	1
valid_sources[0x3c]	24639	1			T9	1		T43	4		T44	1
valid_sources[0x3d]	26300	1			T16	2		T9	1		T43	6
valid_sources[0x3e]	26450	1			T32	1		T43	8		T58	2
valid_sources[0x3f]	26525	1			T5	1		T28	5		T29	2
valid_sources[0x40]	26763	1			T9	1		T32	2		T26	2
valid_sources[0x41]	26249	1			T32	1		T25	1		T6	6
valid_sources[0x42]	25726	1			T45	1		T20	145		T119	1
valid_sources[0x43]	25725	1			T16	1		T14	3		T44	2
valid_sources[0x44]	27772	1			T9	1		T25	1		T23	1
valid_sources[0x45]	25580	1			T9	1		T32	2		T25	1
valid_sources[0x46]	25274	1			T5	1		T9	1		T46	4
valid_sources[0x47]	25013	1			T45	4		T35	1		T29	1
valid_sources[0x48]	28265	1			T5	1		T16	2		T9	1
valid_sources[0x49]	26218	1			T2	2		T14	1		T25	1
valid_sources[0x4a]	25048	1			T2	2		T5	1		T43	6
valid_sources[0x4b]	24204	1			T1	22		T20	148		T119	1
valid_sources[0x4c]	26914	1			T16	1		T13	1		T32	1
valid_sources[0x4d]	25640	1			T32	1		T26	1		T43	1
valid_sources[0x4e]	25936	1			T26	1		T43	8		T44	2
valid_sources[0x4f]	25954	1			T5	1		T46	4		T34	1
valid_sources[0x50]	24836	1			T9	2		T43	7		T45	1
valid_sources[0x51]	26934	1			T5	1		T16	1		T43	7
valid_sources[0x52]	26299	1			T20	141		T119	2		T120	6
valid_sources[0x53]	26413	1			T3	66		T5	1		T32	2
valid_sources[0x54]	25952	1			T56	3		T43	18		T58	1
valid_sources[0x55]	26143	1			T5	2		T14	1		T28	1
valid_sources[0x56]	26110	1			T8	92		T9	1		T44	4
valid_sources[0x57]	24659	1			T9	1		T14	1		T43	9
valid_sources[0x58]	26769	1			T5	1		T16	1		T44	1
valid_sources[0x59]	25642	1			T34	2		T26	1		T43	1
valid_sources[0x5a]	25842	1			T2	1		T5	1		T16	2
valid_sources[0x5b]	27261	1			T2	1		T43	3		T44	3
valid_sources[0x5c]	25456	1			T2	1		T25	1		T43	6
valid_sources[0x5d]	27496	1			T5	1		T25	1		T26	1
valid_sources[0x5e]	26559	1			T1	24		T5	1		T56	1
valid_sources[0x5f]	27253	1			T2	1		T9	1		T13	24
valid_sources[0x60]	26524	1			T1	31		T34	1		T57	3
valid_sources[0x61]	26179	1			T5	1		T25	1		T43	1
valid_sources[0x62]	25850	1			T26	1		T43	2		T44	3
valid_sources[0x63]	26723	1			T5	1		T43	4		T23	1
valid_sources[0x64]	25731	1			T1	16		T5	1		T28	4
valid_sources[0x65]	28084	1			T43	1		T44	1		T35	2
valid_sources[0x66]	24989	1			T5	1		T43	17		T44	1
valid_sources[0x67]	25731	1			T43	3		T20	157		T119	1
valid_sources[0x68]	25184	1			T1	3		T2	1		T9	1
valid_sources[0x69]	25671	1			T5	1		T9	1		T43	1
valid_sources[0x6a]	24912	1			T43	1		T44	1		T20	144
valid_sources[0x6b]	27333	1			T5	1		T46	1		T57	5
valid_sources[0x6c]	25351	1			T32	1		T43	3		T45	1
valid_sources[0x6d]	26711	1			T2	4		T5	1		T34	2
valid_sources[0x6e]	26124	1			T16	1		T9	1		T14	3
valid_sources[0x6f]	24624	1			T43	1		T20	151		T119	2
valid_sources[0x70]	26976	1			T9	1		T14	1		T32	1
valid_sources[0x71]	26184	1			T44	1		T45	8		T7	2
valid_sources[0x72]	26945	1			T16	1		T9	1		T30	78
valid_sources[0x73]	26372	1			T5	1		T32	1		T43	3
valid_sources[0x74]	26590	1			T9	1		T43	6		T44	1
valid_sources[0x75]	26208	1			T9	1		T43	4		T57	1
valid_sources[0x76]	27529	1			T9	1		T43	4		T44	3
valid_sources[0x77]	26470	1			T26	1		T43	1		T44	1
valid_sources[0x78]	25140	1			T9	1		T13	9		T44	4
valid_sources[0x79]	27125	1			T24	1		T20	149		T119	3
valid_sources[0x7a]	26700	1			T46	5		T26	1		T43	5
valid_sources[0x7b]	25461	1			T9	1		T43	6		T45	1
valid_sources[0x7c]	24615	1			T14	1		T32	1		T33	1
valid_sources[0x7d]	26322	1			T14	1		T26	1		T43	1
valid_sources[0x7e]	29364	1			T5	1		T14	1		T32	1
valid_sources[0x7f]	26580	1			T9	1		T43	15		T44	1
valid_sources[0x80]	27015	1			T9	2		T32	1		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1529240

1

T1

90

T2

3

T3

3

values[0x0]

all_enables

biggest_size

2275881

1

T1

5

T2

4

T3

4

values[0x1]

all_enables

biggest_size

2273107

1

T1

2

T2

1

T8

38