Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	0	40	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	0	40	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1634	1			T8	2		T9	1		T13	4
non_zero_bins[1]	1102	1			T8	5		T9	5		T13	1
zero	7301	1			T2	3		T3	3		T4	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	2970	1			T2	1		T32	1		T33	1
gen	3522	1			T2	1		T3	2		T8	2
res	177	1			T8	3		T9	2		T13	2
ins	3368	1			T2	1		T3	1		T8	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

7371

1

T2

3

T8

5

T4

2

mubi_true

2666

1

T3

3

T8

2

T16

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

5075

1

T2

1

T3

1

T8

6

pass

4962

1

T2

2

T3

2

T8

1

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	0	40	100.00
Automatically Generated Cross Bins	40	0	40	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	1091	1			T43	6		T23	1		T44	2
uni	zero	fail	mubi_true	383	1			T56	1		T43	1		T57	1
uni	zero	pass	mubi_false	1132	1			T2	1		T32	1		T33	1
uni	zero	pass	mubi_true	364	1			T43	1		T44	1		T20	3
gen	non_zero_bins[0]	fail	mubi_false	215	1			T20	2		T21	3		T22	4
gen	non_zero_bins[0]	fail	mubi_true	203	1			T13	1		T23	1		T7	1
gen	non_zero_bins[0]	pass	mubi_false	230	1			T43	1		T44	1		T20	1
gen	non_zero_bins[0]	pass	mubi_true	170	1			T13	1		T27	2		T43	2
gen	non_zero_bins[1]	fail	mubi_false	143	1			T32	1		T30	2		T43	2
gen	non_zero_bins[1]	fail	mubi_true	138	1			T8	1		T9	1		T43	2
gen	non_zero_bins[1]	pass	mubi_false	158	1			T20	1		T21	7		T22	1
gen	non_zero_bins[1]	pass	mubi_true	139	1			T8	1		T9	1		T43	3
gen	zero	fail	mubi_false	896	1			T4	1		T28	2		T33	1
gen	zero	fail	mubi_true	157	1			T3	1		T16	1		T17	1
gen	zero	pass	mubi_false	920	1			T2	1		T46	1		T26	1
gen	zero	pass	mubi_true	153	1			T3	1		T16	1		T17	1
res	non_zero_bins[0]	fail	mubi_false	18	1			T13	2		T90	2		T123	2
res	non_zero_bins[0]	fail	mubi_true	23	1			T27	5		T30	2		T41	2
res	non_zero_bins[0]	pass	mubi_false	20	1			T28	4		T90	1		T124	1
res	non_zero_bins[0]	pass	mubi_true	19	1			T30	1		T41	2		T84	1
res	non_zero_bins[1]	fail	mubi_false	16	1			T8	3		T294	1		T84	2
res	non_zero_bins[1]	fail	mubi_true	13	1			T9	1		T10	2		T77	2
res	non_zero_bins[1]	pass	mubi_false	14	1			T294	2		T76	1		T62	1
res	non_zero_bins[1]	pass	mubi_true	11	1			T9	1		T77	1		T263	1
res	zero	fail	mubi_false	18	1			T7	1		T149	1		T295	3
res	zero	fail	mubi_true	7	1			T7	1		T296	2		T297	1
res	zero	pass	mubi_false	9	1			T149	2		T295	1		T155	1
res	zero	pass	mubi_true	9	1			T41	1		T296	1		T297	2
ins	non_zero_bins[0]	fail	mubi_false	191	1			T8	2		T30	1		T43	1
ins	non_zero_bins[0]	fail	mubi_true	186	1			T9	1		T43	3		T44	1
ins	non_zero_bins[0]	pass	mubi_false	189	1			T32	1		T28	1		T23	1
ins	non_zero_bins[0]	pass	mubi_true	170	1			T43	2		T20	1		T21	4
ins	non_zero_bins[1]	fail	mubi_false	121	1			T27	1		T21	5		T117	1
ins	non_zero_bins[1]	fail	mubi_true	103	1			T9	1		T21	1		T22	5
ins	non_zero_bins[1]	pass	mubi_false	122	1			T43	3		T45	1		T21	3
ins	non_zero_bins[1]	pass	mubi_true	124	1			T13	1		T43	1		T20	1
ins	zero	fail	mubi_false	992	1			T2	1		T27	1		T46	1
ins	zero	fail	mubi_true	161	1			T13	1		T17	1		T25	1
ins	zero	pass	mubi_false	876	1			T4	1		T5	1		T33	1
ins	zero	pass	mubi_true	133	1			T3	1		T16	1		T43	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded