SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 16 | 1 | T270 | 2 | T130 | 1 | T92 | 2 | ||||
others[1] | 3 | 1 | T299 | 1 | T86 | 2 | - | - | ||||
others[2] | 9 | 1 | T73 | 2 | T300 | 1 | T301 | 1 | ||||
others[3] | 20 | 1 | T2 | 1 | T269 | 2 | T129 | 1 | ||||
false | 1004 | 1 | T2 | 1 | T3 | 3 | T8 | 2 | ||||
true | 355 | 1 | T8 | 5 | T5 | 3 | T9 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T302 | 2 | T303 | 2 | - | - | ||||
others[1] | 8 | 1 | T67 | 2 | T300 | 1 | T304 | 1 | ||||
others[2] | 9 | 1 | T2 | 1 | T129 | 1 | T130 | 1 | ||||
others[3] | 10 | 1 | T3 | 2 | T268 | 2 | T305 | 1 | ||||
false | 1143 | 1 | T2 | 1 | T3 | 1 | T8 | 7 | ||||
true | 233 | 1 | T24 | 1 | T59 | 2 | T38 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 2 | 1 | T305 | 1 | T306 | 1 | - | - | ||||
others[1] | 5 | 1 | T25 | 1 | T299 | 1 | T301 | 1 | ||||
others[2] | 5 | 1 | T307 | 1 | T308 | 1 | T309 | 1 | ||||
others[3] | 7 | 1 | T2 | 1 | T16 | 1 | T17 | 1 | ||||
false | 975 | 1 | T2 | 1 | T3 | 1 | T8 | 5 | ||||
true | 413 | 1 | T3 | 2 | T8 | 2 | T4 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8 | 1 | T91 | 2 | T310 | 2 | T311 | 2 | ||||
others[1] | 5 | 1 | T130 | 1 | T304 | 1 | T267 | 2 | ||||
others[2] | 3 | 1 | T2 | 1 | T312 | 2 | - | - | ||||
others[3] | 11 | 1 | T83 | 2 | T129 | 1 | T300 | 1 | ||||
false | 546 | 1 | T8 | 5 | T4 | 1 | T5 | 5 | ||||
true | 834 | 1 | T2 | 1 | T3 | 3 | T8 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |