Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	100.00		96.30	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	99.26	100.00	100.00		96.30	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	100.00		96.30	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	100.00		96.30	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	110	100.00
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	1	1
157	1	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T24,T59,T38
1	1	0	1	Covered	T24,T59,T38
1	1	1	0	Covered	T1,T2,T3
1	1	1	1	Covered	T1,T8,T5

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T38,T60
1	1	Covered	T24,T59,T38

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T9,T13
1	1	Covered	T8,T5,T9

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	52	96.30
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T8,T9,T13
AutoCaptGenCnt	162	Covered	T8,T9,T13
AutoCaptReseedCnt	160	Covered	T8,T9,T13
AutoDispatch	142	Covered	T8,T9,T13
AutoFirstAckWait	135	Covered	T8,T5,T9
AutoLoadIns	90	Covered	T8,T5,T9
AutoSendGenCmd	170	Covered	T8,T9,T13
AutoSendReseedCmd	184	Covered	T8,T9,T13
BootCaptGenCnt	106	Covered	T24,T59,T38
BootDone	126	Covered	T24,T59,T38
BootGenAckWait	116	Covered	T24,T59,T38
BootInsAckWait	102	Covered	T24,T59,T38
BootLoadGen	98	Covered	T24,T59,T38
BootLoadIns	88	Covered	T24,T59,T38
BootPulse	121	Covered	T24,T59,T38
BootSendGenCmd	111	Covered	T24,T59,T38
Error	206	Covered	T1,T5,T14
Idle	157	Covered	T1,T2,T3
SWPortMode	93	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T8,T9,T13
AutoAckWait->Error	206	Covered	T145,T53,T146
AutoAckWait->Idle	229	Covered	T8,T9,T13
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T8,T9,T13
AutoCaptGenCnt->Error	206	Covered	T147
AutoCaptGenCnt->Idle	229	Covered	T84,T76,T148
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T8,T9,T13
AutoCaptReseedCnt->Error	206	Not Covered
AutoCaptReseedCnt->Idle	229	Covered	T27,T90,T149
AutoDispatch->AutoCaptGenCnt	162	Covered	T8,T9,T13
AutoDispatch->AutoCaptReseedCnt	160	Covered	T8,T9,T13
AutoDispatch->Error	206	Covered	T105,T150,T151
AutoDispatch->Idle	157	Covered	T13,T41,T10
AutoFirstAckWait->AutoDispatch	142	Covered	T8,T9,T13
AutoFirstAckWait->Error	206	Covered	T5,T152,T153
AutoFirstAckWait->Idle	229	Covered	T30,T154,T155
AutoLoadIns->AutoFirstAckWait	135	Covered	T8,T5,T9
AutoLoadIns->Error	206	Covered	T6,T156,T157
AutoLoadIns->Idle	229	Covered	T77,T63,T158
AutoSendGenCmd->AutoAckWait	177	Covered	T8,T9,T13
AutoSendGenCmd->Error	206	Not Covered
AutoSendGenCmd->Idle	229	Covered	T62,T159,T98
AutoSendReseedCmd->AutoAckWait	191	Covered	T8,T9,T13
AutoSendReseedCmd->Error	206	Covered	T160,T161
AutoSendReseedCmd->Idle	229	Covered	T8,T9,T40
BootCaptGenCnt->BootSendGenCmd	111	Covered	T24,T59,T38
BootCaptGenCnt->Error	206	Covered	T162
BootCaptGenCnt->Idle	229	Covered	T59,T85,T93
BootDone->Error	206	Covered	T49,T50,T163
BootDone->Idle	229	Covered	T80,T74,T132
BootGenAckWait->BootPulse	121	Covered	T24,T59,T38
BootGenAckWait->Error	206	Covered	T164,T165
BootGenAckWait->Idle	229	Covered	T89,T96,T139
BootInsAckWait->BootCaptGenCnt	106	Covered	T24,T59,T38
BootInsAckWait->Error	206	Covered	T166,T167,T168
BootInsAckWait->Idle	229	Covered	T60,T125,T95
BootLoadGen->BootInsAckWait	102	Covered	T24,T59,T38
BootLoadGen->Error	206	Covered	T169
BootLoadGen->Idle	229	Covered	T82,T75,T170
BootLoadIns->BootLoadGen	98	Covered	T24,T59,T38
BootLoadIns->Error	206	Covered	T171,T172,T173
BootLoadIns->Idle	229	Covered	T38,T81,T94
BootPulse->BootDone	126	Covered	T24,T59,T38
BootPulse->Error	206	Covered	T174,T175
BootPulse->Idle	229	Covered	T68,T87,T141
BootSendGenCmd->BootGenAckWait	116	Covered	T24,T59,T38
BootSendGenCmd->Error	206	Covered	T176,T177
BootSendGenCmd->Idle	229	Covered	T88,T178,T179
Idle->AutoLoadIns	90	Covered	T8,T5,T9
Idle->BootLoadIns	88	Covered	T24,T59,T38
Idle->Error	206	Covered	T1,T18,T19
Idle->SWPortMode	93	Covered	T1,T2,T3
SWPortMode->Error	206	Covered	T1,T14,T15
SWPortMode->Idle	229	Covered	T1,T4,T34

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	38	100.00
IF	62	2	2	100.00
CASE	85	33	33	100.00
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T5,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T59,T60,T125
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T59,T38
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T5,T9
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T8,T5,T9
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T13
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T5,T9
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T13
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T10,T123,T124
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T9,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T8,T9,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T8,T9,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T8,T9,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T9,T13
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T9,T13
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T46,T26

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	239997211	122630	0	0
FpvSecCmErrorStEscalate_A	239997211	123386	0	0
u_state_regs_A	239960507	239832767	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	122630	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	697	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1058	0	0
T36	0	1081	0	0
T46	0	588	0	0
T119	0	1036	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	123386	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	698	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1059	0	0
T36	0	1082	0	0
T46	0	589	0	0
T119	0	1037	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239960507	239832767	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1810	1641	0	0
T5	1819	1634	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	562	432	0	0
T16	2002	1940	0	0