Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.38	100.00	86.14			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T8
DataWait	75	Covered	T2,T3,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T41,T68,T87
AckPls->Error	99	Covered	T131,T118,T245
AckPls->Idle	85	Covered	T2,T3,T8
DataWait->AckPls	80	Covered	T2,T3,T8
DataWait->Disabled	107	Covered	T60,T89,T84
DataWait->Error	99	Covered	T49,T246,T163
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T8
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T8
Idle	-	1	0	-	Covered	T2,T3,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T8
DataWait	-	-	-	0	Covered	T2,T3,T8
AckPls	-	-	-	-	Covered	T2,T3,T8
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1679980477	871710	0	0
FpvSecCmErrorStEscalate_A	1679980477	877002	0	0
u_state_regs_A	1679943773	1679049593	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679980477	871710	0	0
T1	112259	36400	0	0
T2	7280	0	0	0
T3	10766	0	0	0
T4	12768	0	0	0
T5	13566	7440	0	0
T6	0	2820	0	0
T7	0	5229	0	0
T8	18445	0	0	0
T9	12656	0	0	0
T13	14721	0	0	0
T14	5145	2933	0	0
T15	0	5495	0	0
T16	14014	0	0	0
T26	0	7756	0	0
T36	0	7917	0	0
T46	0	4466	0	0
T119	0	7602	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679980477	877002	0	0
T1	112259	37030	0	0
T2	7280	0	0	0
T3	10766	0	0	0
T4	12768	0	0	0
T5	13566	7447	0	0
T6	0	2827	0	0
T7	0	5236	0	0
T8	18445	0	0	0
T9	12656	0	0	0
T13	14721	0	0	0
T14	5145	2940	0	0
T15	0	5502	0	0
T16	14014	0	0	0
T26	0	7763	0	0
T36	0	7924	0	0
T46	0	4473	0	0
T119	0	7609	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1679943773	1679049593	0	0
T1	112259	61005	0	0
T2	7280	6671	0	0
T3	10766	10185	0	0
T4	12754	11571	0	0
T5	13447	12152	0	0
T8	18445	17885	0	0
T9	12656	12110	0	0
T13	14721	14364	0	0
T14	4972	4062	0	0
T16	14014	13580	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T30,T29,T41
DataWait	75	Covered	T30,T29,T41
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T30,T29,T41
DataWait->AckPls	80	Covered	T30,T29,T41
DataWait->Disabled	107	Covered	T95,T96,T98
DataWait->Error	99	Covered	T247,T53,T248
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T30,T29,T41
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T29,T41
Idle	-	1	0	-	Covered	T30,T29,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T29,T41
DataWait	-	-	-	0	Covered	T30,T29,T41
AckPls	-	-	-	-	Covered	T30,T29,T41
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	124780	0	0
FpvSecCmErrorStEscalate_A	239997211	125536	0	0
u_state_regs_A	239997211	239869471	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	124780	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	125536	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T4
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T131,T118,T249
AckPls->Idle	85	Covered	T2,T3,T4
DataWait->AckPls	80	Covered	T2,T3,T4
DataWait->Disabled	107	Covered	T185,T250,T251
DataWait->Error	99	Covered	T49,T246,T163
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T210,T18
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T14,T46,T26

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T4
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T4
DataWait	-	-	-	0	Covered	T2,T3,T5
AckPls	-	-	-	-	Covered	T2,T3,T4
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	123030	0	0
FpvSecCmErrorStEscalate_A	239997211	123786	0	0
u_state_regs_A	239960507	239832767	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	123030	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1020	0	0
T6	0	360	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	123786	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1021	0	0
T6	0	361	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239960507	239832767	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1810	1641	0	0
T5	1819	1634	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	562	432	0	0
T16	2002	1940	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T8,T16,T9
DataWait	75	Covered	T8,T16,T9
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T136
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T8,T16,T9
DataWait->AckPls	80	Covered	T8,T16,T9
DataWait->Disabled	107	Covered	T60,T148
DataWait->Error	99	Covered	T252,T253,T254
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T8,T16,T9
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T8,T16,T9
Idle	-	1	0	-	Covered	T8,T16,T9
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T8,T16,T9
DataWait	-	-	-	0	Covered	T8,T16,T9
AckPls	-	-	-	-	Covered	T8,T16,T9
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	124780	0	0
FpvSecCmErrorStEscalate_A	239997211	125536	0	0
u_state_regs_A	239997211	239869471	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	124780	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	125536	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17,T25,T26
DataWait	75	Covered	T17,T25,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T255
AckPls->Idle	85	Covered	T17,T25,T26
DataWait->AckPls	80	Covered	T17,T25,T26
DataWait->Disabled	107	Covered	T84,T256,T257
DataWait->Error	99	Covered	T258,T259,T260
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T17,T25,T26
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T17,T25,T26
Idle	-	1	0	-	Covered	T17,T25,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T17,T25,T26
DataWait	-	-	-	0	Covered	T17,T25,T23
AckPls	-	-	-	-	Covered	T17,T25,T26
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	124780	0	0
FpvSecCmErrorStEscalate_A	239997211	125536	0	0
u_state_regs_A	239997211	239869471	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	124780	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	125536	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T13,T24,T29
DataWait	75	Covered	T13,T24,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T41,T261
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T13,T24,T29
DataWait->AckPls	80	Covered	T13,T24,T29
DataWait->Disabled	107	Covered	T89,T76,T262
DataWait->Error	99	Covered	T119,T47,T50
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T13,T24,T29
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T13,T24,T29
Idle	-	1	0	-	Covered	T13,T24,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T13,T24,T29
DataWait	-	-	-	0	Covered	T13,T24,T29
AckPls	-	-	-	-	Covered	T13,T24,T29
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	124780	0	0
FpvSecCmErrorStEscalate_A	239997211	125536	0	0
u_state_regs_A	239997211	239869471	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	124780	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	125536	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T23,T24,T29
DataWait	75	Covered	T23,T24,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T68
AckPls->Error	99	Covered	T245
AckPls->Idle	85	Covered	T23,T24,T29
DataWait->AckPls	80	Covered	T23,T24,T29
DataWait->Disabled	107	Covered	T62,T159,T263
DataWait->Error	99	Covered	T166,T264,T164
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T23,T24,T29
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T23,T24,T29
Idle	-	1	0	-	Covered	T23,T24,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T23,T24,T29
DataWait	-	-	-	0	Covered	T23,T24,T29
AckPls	-	-	-	-	Covered	T23,T24,T29
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	124780	0	0
FpvSecCmErrorStEscalate_A	239997211	125536	0	0
u_state_regs_A	239997211	239869471	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	124780	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	125536	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T8,T4,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T27,T28,T23
DataWait	75	Covered	T27,T28,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T1,T5,T14
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T87,T265
AckPls->Error	99	Covered	T266
AckPls->Idle	85	Covered	T27,T28,T23
DataWait->AckPls	80	Covered	T27,T28,T23
DataWait->Disabled	107	Covered	T85,T88,T139
DataWait->Error	99	Covered	T153
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T1,T18,T19
EndPointClear->Disabled	107	Covered	T43,T45,T38
EndPointClear->Error	99	Covered	T1,T6,T209
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T27,T28,T23
Idle->Disabled	107	Covered	T1,T8,T4
Idle->Error	99	Covered	T5,T14,T46

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T27,T28,T23
Idle	-	1	0	-	Covered	T27,T28,T23
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T27,T28,T23
DataWait	-	-	-	0	Covered	T27,T28,T23
AckPls	-	-	-	-	Covered	T27,T28,T23
Error	-	-	-	-	Covered	T1,T5,T14
default	-	-	-	-	Covered	T1,T18,T19

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T14
0	1	Covered	T8,T4,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

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Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	239997211	124780	0	0
FpvSecCmErrorStEscalate_A	239997211	125536	0	0
u_state_regs_A	239997211	239869471	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	124780	0	0
T1	16037	5200	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1070	0	0
T6	0	410	0	0
T7	0	747	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	419	0	0
T15	0	785	0	0
T16	2002	0	0	0
T26	0	1108	0	0
T36	0	1131	0	0
T46	0	638	0	0
T119	0	1086	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	125536	0	0
T1	16037	5290	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	1071	0	0
T6	0	411	0	0
T7	0	748	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	420	0	0
T15	0	786	0	0
T16	2002	0	0	0
T26	0	1109	0	0
T36	0	1132	0	0
T46	0	639	0	0
T119	0	1087	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0