Line Coverage for Module :
prim_arbiter_ppc
| Line No. | Total | Covered | Percent |
TOTAL | | 20 | 19 | 95.00 |
CONT_ASSIGN | 55 | 0 | 0 | |
CONT_ASSIGN | 75 | 1 | 1 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
ALWAYS | 82 | 3 | 3 | 100.00 |
CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
ALWAYS | 96 | 6 | 6 | 100.00 |
CONT_ASSIGN | 120 | 1 | 0 | 0.00 |
ALWAYS | 124 | 4 | 4 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
55 |
|
unreachable |
75 |
1 |
1 |
76 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
94 |
1 |
1 |
96 |
1 |
1 |
97 |
1 |
1 |
98 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
103 |
1 |
1 |
|
|
|
MISSING_ELSE |
120 |
0 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
|
|
|
MISSING_ELSE |
Cond Coverage for Module :
prim_arbiter_ppc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 76
EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T8 |
LINE 84
EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
----------------1--------------- -------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T8,T16,T9 |
1 | 0 | Covered | T1,T2,T3 |
LINE 90
EXPRESSION (ready_i ? gen_normal_case.winner : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T3,T8 |
LINE 98
EXPRESSION (valid_o && ready_i)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T8,T4 |
1 | 0 | Covered | T1,T2,T8 |
1 | 1 | Covered | T2,T3,T8 |
LINE 101
EXPRESSION (valid_o && ((!ready_i)))
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T8 |
Branch Coverage for Module :
prim_arbiter_ppc
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
76 |
2 |
2 |
100.00 |
TERNARY |
90 |
2 |
2 |
100.00 |
IF |
96 |
4 |
4 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 76 ((|gen_normal_case.masked_req)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 90 (ready_i) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T3,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 96 if ((!rst_ni))
-2-: 98 if ((valid_o && ready_i))
-3-: 101 if ((valid_o && (!ready_i)))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T3,T8 |
0 |
0 |
1 |
Covered |
T1,T2,T8 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if (gen_normal_case.winner[i])
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_arbiter_ppc
Assertion Details
CheckHotOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
239869471 |
0 |
0 |
T1 |
16037 |
8715 |
0 |
0 |
T2 |
1040 |
953 |
0 |
0 |
T3 |
1538 |
1455 |
0 |
0 |
T4 |
1824 |
1655 |
0 |
0 |
T5 |
1938 |
1753 |
0 |
0 |
T8 |
2635 |
2555 |
0 |
0 |
T9 |
1808 |
1730 |
0 |
0 |
T13 |
2103 |
2052 |
0 |
0 |
T14 |
735 |
605 |
0 |
0 |
T16 |
2002 |
1940 |
0 |
0 |
CheckNGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
564 |
564 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
GntImpliesReady_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
2773 |
0 |
0 |
T2 |
1040 |
1 |
0 |
0 |
T3 |
1538 |
2 |
0 |
0 |
T4 |
1824 |
1 |
0 |
0 |
T5 |
1938 |
0 |
0 |
0 |
T8 |
2635 |
1 |
0 |
0 |
T9 |
1808 |
1 |
0 |
0 |
T13 |
2103 |
1 |
0 |
0 |
T14 |
735 |
0 |
0 |
0 |
T16 |
2002 |
2 |
0 |
0 |
T17 |
1503 |
2 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
GntImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
2773 |
0 |
0 |
T2 |
1040 |
1 |
0 |
0 |
T3 |
1538 |
2 |
0 |
0 |
T4 |
1824 |
1 |
0 |
0 |
T5 |
1938 |
0 |
0 |
0 |
T8 |
2635 |
1 |
0 |
0 |
T9 |
1808 |
1 |
0 |
0 |
T13 |
2103 |
1 |
0 |
0 |
T14 |
735 |
0 |
0 |
0 |
T16 |
2002 |
2 |
0 |
0 |
T17 |
1503 |
2 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
GrantKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
239869471 |
0 |
0 |
T1 |
16037 |
8715 |
0 |
0 |
T2 |
1040 |
953 |
0 |
0 |
T3 |
1538 |
1455 |
0 |
0 |
T4 |
1824 |
1655 |
0 |
0 |
T5 |
1938 |
1753 |
0 |
0 |
T8 |
2635 |
2555 |
0 |
0 |
T9 |
1808 |
1730 |
0 |
0 |
T13 |
2103 |
2052 |
0 |
0 |
T14 |
735 |
605 |
0 |
0 |
T16 |
2002 |
1940 |
0 |
0 |
IdxKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
239869471 |
0 |
0 |
T1 |
16037 |
8715 |
0 |
0 |
T2 |
1040 |
953 |
0 |
0 |
T3 |
1538 |
1455 |
0 |
0 |
T4 |
1824 |
1655 |
0 |
0 |
T5 |
1938 |
1753 |
0 |
0 |
T8 |
2635 |
2555 |
0 |
0 |
T9 |
1808 |
1730 |
0 |
0 |
T13 |
2103 |
2052 |
0 |
0 |
T14 |
735 |
605 |
0 |
0 |
T16 |
2002 |
1940 |
0 |
0 |
IndexIsCorrect_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
2773 |
0 |
0 |
T2 |
1040 |
1 |
0 |
0 |
T3 |
1538 |
2 |
0 |
0 |
T4 |
1824 |
1 |
0 |
0 |
T5 |
1938 |
0 |
0 |
0 |
T8 |
2635 |
1 |
0 |
0 |
T9 |
1808 |
1 |
0 |
0 |
T13 |
2103 |
1 |
0 |
0 |
T14 |
735 |
0 |
0 |
0 |
T16 |
2002 |
2 |
0 |
0 |
T17 |
1503 |
2 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
LockArbDecision_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
216433 |
0 |
0 |
T1 |
16037 |
4610 |
0 |
0 |
T2 |
1040 |
12 |
0 |
0 |
T3 |
1538 |
0 |
0 |
0 |
T4 |
1824 |
0 |
0 |
0 |
T5 |
1938 |
1078 |
0 |
0 |
T6 |
0 |
411 |
0 |
0 |
T8 |
2635 |
40 |
0 |
0 |
T9 |
1808 |
80 |
0 |
0 |
T13 |
2103 |
56 |
0 |
0 |
T14 |
735 |
420 |
0 |
0 |
T16 |
2002 |
0 |
0 |
0 |
T27 |
0 |
78 |
0 |
0 |
T32 |
0 |
277 |
0 |
0 |
NoReadyValidNoGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
239596994 |
0 |
0 |
T1 |
16037 |
4015 |
0 |
0 |
T2 |
1040 |
940 |
0 |
0 |
T3 |
1538 |
1402 |
0 |
0 |
T4 |
1824 |
1643 |
0 |
0 |
T5 |
1938 |
674 |
0 |
0 |
T8 |
2635 |
1923 |
0 |
0 |
T9 |
1808 |
1246 |
0 |
0 |
T13 |
2103 |
1358 |
0 |
0 |
T14 |
735 |
184 |
0 |
0 |
T16 |
2002 |
1872 |
0 |
0 |
ReadyAndValidImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
2773 |
0 |
0 |
T2 |
1040 |
1 |
0 |
0 |
T3 |
1538 |
2 |
0 |
0 |
T4 |
1824 |
1 |
0 |
0 |
T5 |
1938 |
0 |
0 |
0 |
T8 |
2635 |
1 |
0 |
0 |
T9 |
1808 |
1 |
0 |
0 |
T13 |
2103 |
1 |
0 |
0 |
T14 |
735 |
0 |
0 |
0 |
T16 |
2002 |
2 |
0 |
0 |
T17 |
1503 |
2 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
ReqAndReadyImplyGrant_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
2773 |
0 |
0 |
T2 |
1040 |
1 |
0 |
0 |
T3 |
1538 |
2 |
0 |
0 |
T4 |
1824 |
1 |
0 |
0 |
T5 |
1938 |
0 |
0 |
0 |
T8 |
2635 |
1 |
0 |
0 |
T9 |
1808 |
1 |
0 |
0 |
T13 |
2103 |
1 |
0 |
0 |
T14 |
735 |
0 |
0 |
0 |
T16 |
2002 |
2 |
0 |
0 |
T17 |
1503 |
2 |
0 |
0 |
T27 |
0 |
1 |
0 |
0 |
T32 |
0 |
5 |
0 |
0 |
ReqImpliesValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
219920 |
0 |
0 |
T1 |
16037 |
4700 |
0 |
0 |
T2 |
1040 |
13 |
0 |
0 |
T3 |
1538 |
2 |
0 |
0 |
T4 |
1824 |
1 |
0 |
0 |
T5 |
1938 |
1079 |
0 |
0 |
T8 |
2635 |
41 |
0 |
0 |
T9 |
1808 |
81 |
0 |
0 |
T13 |
2103 |
57 |
0 |
0 |
T14 |
735 |
421 |
0 |
0 |
T16 |
2002 |
2 |
0 |
0 |
ReqStaysHighUntilGranted0_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
216433 |
0 |
0 |
T1 |
16037 |
4610 |
0 |
0 |
T2 |
1040 |
12 |
0 |
0 |
T3 |
1538 |
0 |
0 |
0 |
T4 |
1824 |
0 |
0 |
0 |
T5 |
1938 |
1078 |
0 |
0 |
T6 |
0 |
411 |
0 |
0 |
T8 |
2635 |
40 |
0 |
0 |
T9 |
1808 |
80 |
0 |
0 |
T13 |
2103 |
56 |
0 |
0 |
T14 |
735 |
420 |
0 |
0 |
T16 |
2002 |
0 |
0 |
0 |
T27 |
0 |
78 |
0 |
0 |
T32 |
0 |
277 |
0 |
0 |
RoundRobin_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
0 |
0 |
564 |
ValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239997211 |
239869471 |
0 |
0 |
T1 |
16037 |
8715 |
0 |
0 |
T2 |
1040 |
953 |
0 |
0 |
T3 |
1538 |
1455 |
0 |
0 |
T4 |
1824 |
1655 |
0 |
0 |
T5 |
1938 |
1753 |
0 |
0 |
T8 |
2635 |
2555 |
0 |
0 |
T9 |
1808 |
1730 |
0 |
0 |
T13 |
2103 |
2052 |
0 |
0 |
T14 |
735 |
605 |
0 |
0 |
T16 |
2002 |
1940 |
0 |
0 |