Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
81.82	81.82	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	81.82	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.82	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	6	15	71.43

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	6	15	71.43	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	65	1			T18	1		T37	1		T76	1
auto_req_mode	68	1			T8	1		T9	1		T10	1
sw_mode	2660	1			T3	26		T19	1		T20	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

111

1

T18

1

T8

1

T9

1

single

39

1

T121

1

T36

1

T39

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1332	1			T19	1		T20	1		T21	1
auto[2]	8	1			T259	6		T260	1		T261	1
auto[3]	24	1			T262	24		-	-		-	-
auto[4]	146	1			T12	1		T263	55		T264	26
auto[5]	112	1			T18	1		T157	3		T265	27
auto[6]	216	1			T3	26		T9	1		T115	40
auto[7]	955	1			T25	26		T26	51		T37	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	6	15	71.43	6

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[auto_req_mode]	0	1	1
[auto[3]]	[boot_req_mode , auto_req_mode]	--	--	2
[auto[4]]	[boot_req_mode]	0	1	1
[auto[5]]	[auto_req_mode]	0	1	1
[auto[6]]	[boot_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	58	1			T76	1		T61	1		T62	1
auto[1]	auto_req_mode	56	1			T8	1		T10	1		T73	1
auto[1]	sw_mode	1218	1			T19	1		T20	1		T21	1
auto[2]	boot_req_mode	1	1			T261	1		-	-		-	-
auto[2]	sw_mode	7	1			T259	6		T260	1		-	-
auto[3]	sw_mode	24	1			T262	24		-	-		-	-
auto[4]	auto_req_mode	2	1			T12	1		T266	1		-	-
auto[4]	sw_mode	144	1			T263	55		T264	26		T267	5
auto[5]	boot_req_mode	2	1			T18	1		T268	1		-	-
auto[5]	sw_mode	110	1			T157	3		T265	27		T269	8
auto[6]	auto_req_mode	2	1			T9	1		T270	1		-	-
auto[6]	sw_mode	214	1			T3	26		T115	40		T139	50
auto[7]	boot_req_mode	4	1			T37	1		T44	1		T101	1
auto[7]	auto_req_mode	8	1			T11	1		T65	1		T94	1
auto[7]	sw_mode	943	1			T25	26		T26	51		T38	1