Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	531764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4761500

1

T1

4

T2

11

T3

69679

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1371442	1			T1	12		T2	26		T3	19871
values[0x0]	1818340	1			T1	1		T2	5		T3	26476
values[0x1]	2103482	1			T1	9		T2	7		T3	30743

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	257617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5035647

1

T1

9

T2

16

T3

73576

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21928	1			T3	245		T45	3		T17	3
valid_sources[0x01]	20586	1			T3	240		T20	1		T25	202
valid_sources[0x02]	19701	1			T3	167		T51	3		T25	214
valid_sources[0x03]	20502	1			T3	162		T22	2		T8	1
valid_sources[0x04]	20161	1			T3	266		T18	1		T25	207
valid_sources[0x05]	20460	1			T3	334		T25	206		T9	2
valid_sources[0x06]	19103	1			T3	180		T18	1		T20	2
valid_sources[0x07]	20142	1			T3	295		T22	2		T45	1
valid_sources[0x08]	21576	1			T3	234		T18	1		T25	215
valid_sources[0x09]	20920	1			T3	429		T20	1		T17	1
valid_sources[0x0a]	21129	1			T3	296		T22	2		T8	1
valid_sources[0x0b]	21472	1			T3	320		T18	1		T45	2
valid_sources[0x0c]	20154	1			T3	311		T19	8		T25	172
valid_sources[0x0d]	20496	1			T3	229		T18	2		T20	1
valid_sources[0x0e]	20577	1			T3	313		T15	275		T51	1
valid_sources[0x0f]	21575	1			T3	267		T17	2		T54	1
valid_sources[0x10]	20716	1			T3	299		T25	179		T296	1
valid_sources[0x11]	20987	1			T3	316		T25	192		T9	3
valid_sources[0x12]	20745	1			T3	267		T34	3		T25	214
valid_sources[0x13]	19040	1			T3	261		T22	1		T25	202
valid_sources[0x14]	20311	1			T3	285		T19	8		T25	203
valid_sources[0x15]	20309	1			T3	237		T45	2		T25	211
valid_sources[0x16]	19900	1			T3	309		T18	3		T25	195
valid_sources[0x17]	19555	1			T3	261		T25	169		T26	455
valid_sources[0x18]	20451	1			T3	260		T18	1		T4	1
valid_sources[0x19]	21133	1			T3	304		T25	215		T9	3
valid_sources[0x1a]	20625	1			T3	363		T20	1		T25	219
valid_sources[0x1b]	20353	1			T3	385		T20	1		T25	178
valid_sources[0x1c]	22568	1			T3	211		T54	1		T25	218
valid_sources[0x1d]	20365	1			T3	435		T17	1		T51	1
valid_sources[0x1e]	20185	1			T1	1		T3	311		T51	1
valid_sources[0x1f]	20689	1			T3	294		T18	1		T34	3
valid_sources[0x20]	20298	1			T3	264		T8	1		T25	196
valid_sources[0x21]	22461	1			T3	383		T17	1		T8	1
valid_sources[0x22]	20530	1			T3	304		T25	207		T9	1
valid_sources[0x23]	21262	1			T3	343		T22	1		T25	196
valid_sources[0x24]	19418	1			T3	288		T54	1		T25	170
valid_sources[0x25]	20447	1			T3	304		T54	1		T25	198
valid_sources[0x26]	20223	1			T3	291		T19	1		T17	1
valid_sources[0x27]	21689	1			T3	312		T22	1		T34	3
valid_sources[0x28]	23028	1			T3	276		T22	2		T25	201
valid_sources[0x29]	19957	1			T3	228		T25	193		T9	1
valid_sources[0x2a]	22253	1			T3	240		T25	202		T9	2
valid_sources[0x2b]	22016	1			T3	427		T34	1		T25	210
valid_sources[0x2c]	21741	1			T3	275		T18	1		T45	1
valid_sources[0x2d]	20430	1			T3	182		T34	2		T25	187
valid_sources[0x2e]	21761	1			T3	426		T54	1		T25	201
valid_sources[0x2f]	21059	1			T3	219		T18	1		T17	1
valid_sources[0x30]	21091	1			T3	357		T17	2		T55	1
valid_sources[0x31]	20758	1			T3	304		T18	1		T25	216
valid_sources[0x32]	19713	1			T3	318		T18	4		T22	1
valid_sources[0x33]	19277	1			T3	206		T22	1		T25	188
valid_sources[0x34]	21024	1			T3	335		T8	1		T25	209
valid_sources[0x35]	21021	1			T3	427		T25	204		T9	3
valid_sources[0x36]	20538	1			T3	436		T18	3		T17	1
valid_sources[0x37]	21503	1			T3	244		T25	190		T9	3
valid_sources[0x38]	19458	1			T3	272		T18	2		T20	1
valid_sources[0x39]	19268	1			T1	3		T3	311		T25	213
valid_sources[0x3a]	20071	1			T1	1		T3	231		T19	1
valid_sources[0x3b]	21319	1			T3	340		T25	193		T296	1
valid_sources[0x3c]	20210	1			T3	395		T16	37		T34	1
valid_sources[0x3d]	19523	1			T3	269		T18	1		T19	4
valid_sources[0x3e]	20905	1			T3	342		T34	4		T25	216
valid_sources[0x3f]	20588	1			T3	219		T25	198		T9	2
valid_sources[0x40]	20415	1			T3	336		T17	1		T25	196
valid_sources[0x41]	22174	1			T3	328		T51	1		T25	222
valid_sources[0x42]	19619	1			T3	315		T8	1		T25	206
valid_sources[0x43]	21794	1			T3	306		T25	193		T26	349
valid_sources[0x44]	20958	1			T3	268		T25	176		T26	435
valid_sources[0x45]	19800	1			T3	336		T18	1		T8	1
valid_sources[0x46]	18719	1			T3	291		T18	1		T17	1
valid_sources[0x47]	20425	1			T3	421		T25	214		T9	1
valid_sources[0x48]	19220	1			T3	265		T18	1		T25	203
valid_sources[0x49]	22448	1			T3	301		T18	1		T17	1
valid_sources[0x4a]	21476	1			T3	329		T25	205		T9	3
valid_sources[0x4b]	19551	1			T3	242		T18	2		T25	187
valid_sources[0x4c]	20969	1			T3	318		T18	1		T25	217
valid_sources[0x4d]	20596	1			T3	218		T18	1		T4	1
valid_sources[0x4e]	20071	1			T3	213		T19	3		T14	16
valid_sources[0x4f]	21799	1			T3	383		T4	1		T8	1
valid_sources[0x50]	21361	1			T3	332		T18	2		T17	2
valid_sources[0x51]	18980	1			T3	164		T18	2		T34	3
valid_sources[0x52]	21918	1			T3	273		T22	1		T25	190
valid_sources[0x53]	20487	1			T3	235		T18	1		T25	210
valid_sources[0x54]	21353	1			T3	303		T18	1		T25	198
valid_sources[0x55]	21526	1			T3	400		T54	1		T25	239
valid_sources[0x56]	21568	1			T3	299		T18	1		T4	1
valid_sources[0x57]	19824	1			T3	344		T22	1		T8	1
valid_sources[0x58]	21148	1			T3	318		T25	198		T9	3
valid_sources[0x59]	21366	1			T3	254		T25	199		T123	1
valid_sources[0x5a]	20341	1			T3	464		T4	2		T20	1
valid_sources[0x5b]	20931	1			T3	427		T18	1		T4	1
valid_sources[0x5c]	18447	1			T3	240		T17	1		T54	1
valid_sources[0x5d]	21491	1			T3	365		T8	1		T25	197
valid_sources[0x5e]	19836	1			T3	411		T18	1		T25	183
valid_sources[0x5f]	20325	1			T3	234		T17	1		T51	1
valid_sources[0x60]	19036	1			T3	386		T18	2		T17	4
valid_sources[0x61]	20946	1			T3	282		T18	1		T8	1
valid_sources[0x62]	20055	1			T3	392		T19	2		T4	1
valid_sources[0x63]	20766	1			T3	263		T18	1		T25	213
valid_sources[0x64]	20771	1			T3	299		T18	3		T17	1
valid_sources[0x65]	20554	1			T3	388		T25	217		T9	3
valid_sources[0x66]	20334	1			T3	324		T19	2		T20	1
valid_sources[0x67]	20372	1			T3	273		T20	1		T22	1
valid_sources[0x68]	19420	1			T3	215		T8	1		T25	191
valid_sources[0x69]	21134	1			T3	307		T19	3		T22	2
valid_sources[0x6a]	19701	1			T1	4		T3	441		T45	1
valid_sources[0x6b]	20641	1			T3	239		T18	1		T21	1
valid_sources[0x6c]	19308	1			T3	320		T18	1		T25	206
valid_sources[0x6d]	21227	1			T3	322		T17	1		T8	2
valid_sources[0x6e]	19545	1			T3	330		T25	192		T26	360
valid_sources[0x6f]	20168	1			T3	340		T18	3		T34	1
valid_sources[0x70]	19968	1			T3	191		T18	1		T34	1
valid_sources[0x71]	22163	1			T3	189		T4	1		T34	1
valid_sources[0x72]	22635	1			T3	194		T18	1		T25	208
valid_sources[0x73]	21328	1			T3	298		T21	10		T25	186
valid_sources[0x74]	20149	1			T3	270		T18	2		T19	8
valid_sources[0x75]	20233	1			T3	303		T20	1		T21	4
valid_sources[0x76]	20592	1			T3	276		T25	218		T9	3
valid_sources[0x77]	21096	1			T3	312		T18	2		T22	3
valid_sources[0x78]	19033	1			T3	219		T18	2		T25	212
valid_sources[0x79]	20645	1			T3	311		T18	1		T20	1
valid_sources[0x7a]	21898	1			T3	361		T18	1		T25	192
valid_sources[0x7b]	20368	1			T3	259		T18	1		T25	218
valid_sources[0x7c]	20489	1			T3	243		T25	191		T9	5
valid_sources[0x7d]	20920	1			T3	191		T18	2		T45	2
valid_sources[0x7e]	21060	1			T3	329		T25	201		T123	1
valid_sources[0x7f]	21245	1			T3	312		T25	196		T9	4
valid_sources[0x80]	20352	1			T3	240		T45	2		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1198669

1

T1

1

T2

4

T3

17544

values[0x0]

all_enables

biggest_size

1781509

1

T1

1

T2

4

T3

26023

values[0x1]

all_enables

biggest_size

1781322

1

T1

2

T2

3

T3

26112