Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	0	40	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	0	40	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1570	1			T3	7		T8	2		T25	13
non_zero_bins[1]	1169	1			T3	7		T8	4		T25	12
zero	6496	1			T1	2		T2	3		T3	64

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	2666	1			T3	26		T19	1		T20	1
gen	3299	1			T1	1		T2	2		T3	26
res	203	1			T8	3		T9	2		T10	3
ins	3067	1			T1	1		T2	1		T3	26

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6548

1

T1

2

T3

61

T19

2

mubi_true

2687

1

T2

3

T3

17

T18

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

4572

1

T1

1

T2

1

T3

37

pass

4663

1

T1

1

T2

2

T3

41

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	0	40	100.00
Automatically Generated Cross Bins	40	0	40	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	996	1			T3	8		T21	1		T25	18
uni	zero	fail	mubi_true	330	1			T3	4		T20	1		T26	9
uni	zero	pass	mubi_false	997	1			T3	11		T55	1		T25	7
uni	zero	pass	mubi_true	343	1			T3	3		T19	1		T25	1
gen	non_zero_bins[0]	fail	mubi_false	202	1			T3	2		T8	1		T25	2
gen	non_zero_bins[0]	fail	mubi_true	215	1			T3	1		T25	3		T26	3
gen	non_zero_bins[0]	pass	mubi_false	202	1			T3	1		T8	1		T25	1
gen	non_zero_bins[0]	pass	mubi_true	179	1			T25	3		T26	3		T38	1
gen	non_zero_bins[1]	fail	mubi_false	118	1			T3	1		T25	1		T88	1
gen	non_zero_bins[1]	fail	mubi_true	156	1			T3	1		T25	1		T26	2
gen	non_zero_bins[1]	pass	mubi_false	128	1			T25	2		T26	2		T120	1
gen	non_zero_bins[1]	pass	mubi_true	175	1			T3	2		T26	2		T11	10
gen	zero	fail	mubi_false	831	1			T1	1		T3	8		T22	1
gen	zero	fail	mubi_true	147	1			T3	2		T18	1		T16	1
gen	zero	pass	mubi_false	785	1			T3	8		T19	1		T20	1
gen	zero	pass	mubi_true	161	1			T2	2		T4	1		T16	1
res	non_zero_bins[0]	fail	mubi_false	20	1			T41	3		T78	2		T65	1
res	non_zero_bins[0]	fail	mubi_true	33	1			T73	1		T30	2		T36	4
res	non_zero_bins[0]	pass	mubi_false	21	1			T10	3		T78	1		T65	1
res	non_zero_bins[0]	pass	mubi_true	22	1			T73	1		T30	3		T126	1
res	non_zero_bins[1]	fail	mubi_false	19	1			T9	2		T42	3		T275	3
res	non_zero_bins[1]	fail	mubi_true	21	1			T8	2		T11	1		T81	2
res	non_zero_bins[1]	pass	mubi_false	17	1			T180	3		T174	2		T240	2
res	non_zero_bins[1]	pass	mubi_true	24	1			T8	1		T11	1		T81	2
res	zero	fail	mubi_false	9	1			T41	1		T82	3		T92	2
res	zero	fail	mubi_true	6	1			T276	2		T13	1		T250	1
res	zero	pass	mubi_false	7	1			T41	1		T126	1		T163	1
res	zero	pass	mubi_true	4	1			T276	1		T92	1		T13	1
ins	non_zero_bins[0]	fail	mubi_false	174	1			T3	2		T25	2		T9	1
ins	non_zero_bins[0]	fail	mubi_true	175	1			T26	2		T73	1		T115	1
ins	non_zero_bins[0]	pass	mubi_false	170	1			T25	1		T26	5		T10	1
ins	non_zero_bins[0]	pass	mubi_true	157	1			T3	1		T25	1		T26	2
ins	non_zero_bins[1]	fail	mubi_false	121	1			T3	1		T25	2		T26	1
ins	non_zero_bins[1]	fail	mubi_true	131	1			T8	1		T25	3		T26	2
ins	non_zero_bins[1]	pass	mubi_false	122	1			T3	1		T25	2		T26	3
ins	non_zero_bins[1]	pass	mubi_true	137	1			T3	1		T25	1		T26	2
ins	zero	fail	mubi_false	742	1			T3	7		T19	1		T4	1
ins	zero	fail	mubi_true	126	1			T2	1		T18	1		T16	1
ins	zero	pass	mubi_false	867	1			T1	1		T3	11		T21	1
ins	zero	pass	mubi_true	145	1			T3	2		T4	1		T17	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded