Summary for Variable csrng_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for csrng_glen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
1872 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
16 |
glens[1] |
6 |
1 |
|
|
T277 |
1 |
|
T278 |
1 |
|
T279 |
1 |
glens[2] |
6 |
1 |
|
|
T38 |
1 |
|
T11 |
1 |
|
T280 |
1 |
glens[3] |
8 |
1 |
|
|
T121 |
1 |
|
T281 |
1 |
|
T70 |
1 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
1669 |
1 |
|
|
T1 |
1 |
|
T3 |
15 |
|
T18 |
1 |
pass |
1630 |
1 |
|
|
T2 |
2 |
|
T3 |
11 |
|
T19 |
1 |
Summary for Cross csrng_genbits_cross
Samples crossed: csrng_glen csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for csrng_genbits_cross
Bins
csrng_glen | csrng_sts | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
fail |
952 |
1 |
|
|
T1 |
1 |
|
T3 |
8 |
|
T18 |
1 |
glens[0] |
pass |
920 |
1 |
|
|
T2 |
2 |
|
T3 |
8 |
|
T19 |
1 |
glens[1] |
fail |
2 |
1 |
|
|
T278 |
1 |
|
T282 |
1 |
|
- |
- |
glens[1] |
pass |
4 |
1 |
|
|
T277 |
1 |
|
T279 |
1 |
|
T283 |
1 |
glens[2] |
fail |
3 |
1 |
|
|
T11 |
1 |
|
T280 |
1 |
|
T284 |
1 |
glens[2] |
pass |
3 |
1 |
|
|
T38 |
1 |
|
T285 |
1 |
|
T260 |
1 |
glens[3] |
fail |
3 |
1 |
|
|
T121 |
1 |
|
T286 |
1 |
|
T94 |
1 |
glens[3] |
pass |
5 |
1 |
|
|
T281 |
1 |
|
T70 |
1 |
|
T287 |
1 |