SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 95.83 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable | 83.33 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode | 100.00 | 1 | 100 | 1 | 64 | 64 |
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
83.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 1 | 5 | 83.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 1 | 5 | 83.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 6 | 0 | 6 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 1 | 5 | 83.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
others[1] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 6 | 1 | T288 | 1 | T289 | 1 | T290 | 1 | ||||
others[2] | 11 | 1 | T20 | 1 | T34 | 2 | T58 | 1 | ||||
others[3] | 6 | 1 | T16 | 2 | T125 | 1 | T291 | 1 | ||||
false | 589 | 1 | T1 | 1 | T4 | 1 | T22 | 1 | ||||
true | 848 | 1 | T1 | 2 | T2 | 3 | T18 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T68 | 2 | T153 | 1 | T292 | 1 | ||||
others[1] | 11 | 1 | T125 | 1 | T255 | 2 | T290 | 1 | ||||
others[2] | 4 | 1 | T20 | 1 | T289 | 1 | T293 | 2 | ||||
others[3] | 17 | 1 | T58 | 1 | T291 | 1 | T288 | 1 | ||||
false | 1040 | 1 | T1 | 3 | T2 | 3 | T18 | 1 | ||||
true | 384 | 1 | T8 | 4 | T9 | 1 | T10 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 4 | 1 | T294 | 2 | T289 | 1 | T290 | 1 | ||||
others[1] | 8 | 1 | T20 | 1 | T17 | 2 | T125 | 1 | ||||
others[2] | 15 | 1 | T291 | 1 | T153 | 1 | T80 | 2 | ||||
others[3] | 15 | 1 | T2 | 2 | T58 | 1 | T292 | 1 | ||||
false | 1162 | 1 | T1 | 3 | T2 | 1 | T19 | 1 | ||||
true | 256 | 1 | T18 | 1 | T4 | 3 | T14 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
others[0] | 8 | 1 | T58 | 1 | T153 | 1 | T89 | 1 | ||||
others[1] | 5 | 1 | T29 | 1 | T125 | 1 | T295 | 1 | ||||
others[2] | 6 | 1 | T20 | 1 | T114 | 1 | T77 | 1 | ||||
others[3] | 3 | 1 | T54 | 1 | T291 | 1 | T290 | 1 | ||||
false | 1008 | 1 | T1 | 2 | T2 | 1 | T18 | 1 | ||||
true | 430 | 1 | T1 | 1 | T2 | 2 | T4 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |