Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T3,T18,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T18,T19 |
1 | 0 | Covered | T1,T2,T18 |
1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T10,T73 |
1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T18,T19 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T18,T19 |
1 | 0 | Covered | T1,T3,T18 |
1 | 1 | Covered | T3,T18,T19 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T18,T19 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T18 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T3,T18 |
1 | 1 | Covered | T1,T3,T18 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T18 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T18 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T18 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T18 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T18 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T76,T61,T119 |
1 | 1 | Covered | T1,T3,T18 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T3,T18 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T3,T18 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T18 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1542188520 |
171328520 |
0 |
4512 |
T1 |
1950 |
1118 |
0 |
1 |
T2 |
3478 |
0 |
0 |
2 |
T3 |
669633 |
222109 |
0 |
3 |
T4 |
9325 |
0 |
0 |
5 |
T6 |
2294 |
0 |
0 |
1 |
T8 |
2226 |
0 |
0 |
1 |
T9 |
0 |
1085 |
0 |
0 |
T11 |
2678 |
0 |
0 |
1 |
T14 |
9177 |
0 |
0 |
3 |
T16 |
8800 |
1242 |
0 |
5 |
T17 |
3116 |
1164 |
0 |
2 |
T18 |
12385 |
4845 |
0 |
5 |
T19 |
5925 |
1003 |
0 |
5 |
T20 |
4570 |
666 |
0 |
5 |
T21 |
8325 |
1410 |
0 |
5 |
T22 |
5700 |
603 |
0 |
5 |
T25 |
146641 |
0 |
0 |
1 |
T27 |
0 |
1118 |
0 |
0 |
T34 |
0 |
1196 |
0 |
0 |
T37 |
0 |
1176 |
0 |
0 |
T40 |
0 |
1284 |
0 |
0 |
T41 |
0 |
836 |
0 |
0 |
T45 |
4924 |
0 |
0 |
4 |
T54 |
0 |
970 |
0 |
0 |
T55 |
1165 |
993 |
0 |
1 |
T61 |
0 |
79 |
0 |
0 |
T62 |
0 |
907 |
0 |
0 |
T84 |
745 |
0 |
0 |
1 |
T85 |
1709 |
0 |
0 |
1 |
T86 |
1799 |
0 |
0 |
1 |
T106 |
0 |
141 |
0 |
0 |
T126 |
0 |
1302 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1542188520 |
171328520 |
0 |
0 |
T1 |
1950 |
1118 |
0 |
0 |
T2 |
3478 |
0 |
0 |
0 |
T3 |
669633 |
222109 |
0 |
0 |
T4 |
9325 |
0 |
0 |
0 |
T6 |
2294 |
0 |
0 |
0 |
T8 |
2226 |
0 |
0 |
0 |
T9 |
0 |
1085 |
0 |
0 |
T11 |
2678 |
0 |
0 |
0 |
T14 |
9177 |
0 |
0 |
0 |
T16 |
8800 |
1242 |
0 |
0 |
T17 |
3116 |
1164 |
0 |
0 |
T18 |
12385 |
4845 |
0 |
0 |
T19 |
5925 |
1003 |
0 |
0 |
T20 |
4570 |
666 |
0 |
0 |
T21 |
8325 |
1410 |
0 |
0 |
T22 |
5700 |
603 |
0 |
0 |
T25 |
146641 |
0 |
0 |
0 |
T27 |
0 |
1118 |
0 |
0 |
T34 |
0 |
1196 |
0 |
0 |
T37 |
0 |
1176 |
0 |
0 |
T40 |
0 |
1284 |
0 |
0 |
T41 |
0 |
836 |
0 |
0 |
T45 |
4924 |
0 |
0 |
0 |
T54 |
0 |
970 |
0 |
0 |
T55 |
1165 |
993 |
0 |
0 |
T61 |
0 |
79 |
0 |
0 |
T62 |
0 |
907 |
0 |
0 |
T84 |
745 |
0 |
0 |
0 |
T85 |
1709 |
0 |
0 |
0 |
T86 |
1799 |
0 |
0 |
0 |
T106 |
0 |
141 |
0 |
0 |
T126 |
0 |
1302 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 23 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T18 |
1 | 0 | Covered | T3,T18,T19 |
1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T18,T19 |
1 | 0 | Covered | T1,T2,T18 |
1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T10,T73 |
1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
12 |
85.71 |
TERNARY |
141 |
4 |
3 |
75.00 |
TERNARY |
146 |
3 |
2 |
66.67 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
63262 |
0 |
564 |
T1 |
1950 |
38 |
0 |
1 |
T2 |
1739 |
46 |
0 |
1 |
T3 |
223211 |
0 |
0 |
1 |
T4 |
1865 |
0 |
0 |
1 |
T8 |
0 |
413 |
0 |
0 |
T16 |
1760 |
78 |
0 |
1 |
T17 |
0 |
24 |
0 |
0 |
T18 |
2477 |
5 |
0 |
1 |
T19 |
1185 |
0 |
0 |
1 |
T20 |
914 |
0 |
0 |
1 |
T21 |
1665 |
0 |
0 |
1 |
T22 |
1140 |
39 |
0 |
1 |
T27 |
0 |
64 |
0 |
0 |
T34 |
0 |
80 |
0 |
0 |
T54 |
0 |
82 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
63262 |
0 |
0 |
T1 |
1950 |
38 |
0 |
0 |
T2 |
1739 |
46 |
0 |
0 |
T3 |
223211 |
0 |
0 |
0 |
T4 |
1865 |
0 |
0 |
0 |
T8 |
0 |
413 |
0 |
0 |
T16 |
1760 |
78 |
0 |
0 |
T17 |
0 |
24 |
0 |
0 |
T18 |
2477 |
5 |
0 |
0 |
T19 |
1185 |
0 |
0 |
0 |
T20 |
914 |
0 |
0 |
0 |
T21 |
1665 |
0 |
0 |
0 |
T22 |
1140 |
39 |
0 |
0 |
T27 |
0 |
64 |
0 |
0 |
T34 |
0 |
80 |
0 |
0 |
T54 |
0 |
82 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T18,T19 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T18,T19 |
1 | 0 | Covered | T3,T18,T19 |
1 | 1 | Covered | T3,T18,T19 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T18,T19 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T18,T19 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T18,T19 |
1 | 1 | Covered | T3,T18,T19 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T18,T19 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T18,T19 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T18,T19 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T18,T19 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T18,T19 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T119,T127 |
1 | 1 | Covered | T3,T18,T19 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T3,T18,T19 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T18,T19 |
0 |
0 |
1 |
Covered |
T3,T18,T19 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T18,T19 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T18,T19 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
171039398 |
0 |
564 |
T3 |
223211 |
222109 |
0 |
1 |
T4 |
1865 |
0 |
0 |
1 |
T14 |
3059 |
0 |
0 |
1 |
T16 |
1760 |
1242 |
0 |
1 |
T17 |
0 |
1164 |
0 |
0 |
T18 |
2477 |
1467 |
0 |
1 |
T19 |
1185 |
1003 |
0 |
1 |
T20 |
914 |
666 |
0 |
1 |
T21 |
1665 |
1410 |
0 |
1 |
T22 |
1140 |
603 |
0 |
1 |
T45 |
1231 |
0 |
0 |
1 |
T54 |
0 |
970 |
0 |
0 |
T55 |
0 |
993 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
171039398 |
0 |
0 |
T3 |
223211 |
222109 |
0 |
0 |
T4 |
1865 |
0 |
0 |
0 |
T14 |
3059 |
0 |
0 |
0 |
T16 |
1760 |
1242 |
0 |
0 |
T17 |
0 |
1164 |
0 |
0 |
T18 |
2477 |
1467 |
0 |
0 |
T19 |
1185 |
1003 |
0 |
0 |
T20 |
914 |
666 |
0 |
0 |
T21 |
1665 |
1410 |
0 |
0 |
T22 |
1140 |
603 |
0 |
0 |
T45 |
1231 |
0 |
0 |
0 |
T54 |
0 |
970 |
0 |
0 |
T55 |
0 |
993 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T9,T37 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T9,T37 |
1 | 0 | Covered | T18,T27,T9 |
1 | 1 | Covered | T18,T9,T37 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T9,T37 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T18,T27,T9 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T18,T27,T9 |
1 | 1 | Covered | T18,T27,T9 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T27,T9 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T27,T9 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T27,T9 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T27,T9 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T27,T9 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T61,T66,T128 |
1 | 1 | Covered | T18,T27,T9 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T18,T27,T9 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T18,T27,T9 |
0 |
0 |
1 |
Covered |
T18,T27,T9 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T18,T27,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T18,T27,T9 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
44720 |
0 |
564 |
T4 |
1865 |
0 |
0 |
1 |
T9 |
0 |
1085 |
0 |
0 |
T14 |
3059 |
0 |
0 |
1 |
T16 |
1760 |
0 |
0 |
1 |
T17 |
1558 |
0 |
0 |
1 |
T18 |
2477 |
1693 |
0 |
1 |
T19 |
1185 |
0 |
0 |
1 |
T20 |
914 |
0 |
0 |
1 |
T21 |
1665 |
0 |
0 |
1 |
T22 |
1140 |
0 |
0 |
1 |
T27 |
0 |
1118 |
0 |
0 |
T37 |
0 |
1176 |
0 |
0 |
T40 |
0 |
1284 |
0 |
0 |
T41 |
0 |
836 |
0 |
0 |
T45 |
1231 |
0 |
0 |
1 |
T61 |
0 |
79 |
0 |
0 |
T62 |
0 |
907 |
0 |
0 |
T106 |
0 |
141 |
0 |
0 |
T126 |
0 |
1302 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
44720 |
0 |
0 |
T4 |
1865 |
0 |
0 |
0 |
T9 |
0 |
1085 |
0 |
0 |
T14 |
3059 |
0 |
0 |
0 |
T16 |
1760 |
0 |
0 |
0 |
T17 |
1558 |
0 |
0 |
0 |
T18 |
2477 |
1693 |
0 |
0 |
T19 |
1185 |
0 |
0 |
0 |
T20 |
914 |
0 |
0 |
0 |
T21 |
1665 |
0 |
0 |
0 |
T22 |
1140 |
0 |
0 |
0 |
T27 |
0 |
1118 |
0 |
0 |
T37 |
0 |
1176 |
0 |
0 |
T40 |
0 |
1284 |
0 |
0 |
T41 |
0 |
836 |
0 |
0 |
T45 |
1231 |
0 |
0 |
0 |
T61 |
0 |
79 |
0 |
0 |
T62 |
0 |
907 |
0 |
0 |
T106 |
0 |
141 |
0 |
0 |
T126 |
0 |
1302 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T34,T10 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T34,T10 |
1 | 0 | Covered | T1,T18,T34 |
1 | 1 | Covered | T18,T34,T10 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T34,T10 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T18,T34 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T18,T34 |
1 | 1 | Covered | T1,T18,T34 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T34 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T34 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T34 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T18,T34 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T18,T34 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T35,T129 |
1 | 1 | Covered | T1,T18,T34 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T18,T34 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T18,T34 |
0 |
0 |
1 |
Covered |
T1,T18,T34 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T18,T34 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T18,T34 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
44516 |
0 |
564 |
T1 |
1950 |
1118 |
0 |
1 |
T2 |
1739 |
0 |
0 |
1 |
T3 |
223211 |
0 |
0 |
1 |
T4 |
1865 |
0 |
0 |
1 |
T5 |
0 |
602 |
0 |
0 |
T10 |
0 |
848 |
0 |
0 |
T16 |
1760 |
0 |
0 |
1 |
T18 |
2477 |
1685 |
0 |
1 |
T19 |
1185 |
0 |
0 |
1 |
T20 |
914 |
0 |
0 |
1 |
T21 |
1665 |
0 |
0 |
1 |
T22 |
1140 |
0 |
0 |
1 |
T34 |
0 |
1196 |
0 |
0 |
T35 |
0 |
280 |
0 |
0 |
T36 |
0 |
1128 |
0 |
0 |
T43 |
0 |
914 |
0 |
0 |
T68 |
0 |
997 |
0 |
0 |
T69 |
0 |
668 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
44516 |
0 |
0 |
T1 |
1950 |
1118 |
0 |
0 |
T2 |
1739 |
0 |
0 |
0 |
T3 |
223211 |
0 |
0 |
0 |
T4 |
1865 |
0 |
0 |
0 |
T5 |
0 |
602 |
0 |
0 |
T10 |
0 |
848 |
0 |
0 |
T16 |
1760 |
0 |
0 |
0 |
T18 |
2477 |
1685 |
0 |
0 |
T19 |
1185 |
0 |
0 |
0 |
T20 |
914 |
0 |
0 |
0 |
T21 |
1665 |
0 |
0 |
0 |
T22 |
1140 |
0 |
0 |
0 |
T34 |
0 |
1196 |
0 |
0 |
T35 |
0 |
280 |
0 |
0 |
T36 |
0 |
1128 |
0 |
0 |
T43 |
0 |
914 |
0 |
0 |
T68 |
0 |
997 |
0 |
0 |
T69 |
0 |
668 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T18,T9,T37 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T9,T37 |
1 | 0 | Covered | T18,T9,T28 |
1 | 1 | Covered | T18,T9,T37 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T9,T37 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T18,T9,T28 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T18,T9,T28 |
1 | 1 | Covered | T18,T9,T28 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T9,T28 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T9,T28 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T9,T28 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T9,T28 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T9,T28 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T75,T130,T131 |
1 | 1 | Covered | T18,T9,T28 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T18,T9,T28 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T18,T9,T28 |
0 |
0 |
1 |
Covered |
T18,T9,T28 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T18,T9,T28 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T18,T9,T28 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
39594 |
0 |
564 |
T4 |
1865 |
0 |
0 |
1 |
T9 |
0 |
1126 |
0 |
0 |
T14 |
3059 |
0 |
0 |
1 |
T16 |
1760 |
0 |
0 |
1 |
T17 |
1558 |
0 |
0 |
1 |
T18 |
2477 |
1437 |
0 |
1 |
T19 |
1185 |
0 |
0 |
1 |
T20 |
914 |
0 |
0 |
1 |
T21 |
1665 |
0 |
0 |
1 |
T22 |
1140 |
0 |
0 |
1 |
T28 |
0 |
538 |
0 |
0 |
T30 |
0 |
743 |
0 |
0 |
T37 |
0 |
998 |
0 |
0 |
T40 |
0 |
984 |
0 |
0 |
T44 |
0 |
1398 |
0 |
0 |
T45 |
1231 |
0 |
0 |
1 |
T65 |
0 |
1364 |
0 |
0 |
T73 |
0 |
863 |
0 |
0 |
T84 |
0 |
363 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
39594 |
0 |
0 |
T4 |
1865 |
0 |
0 |
0 |
T9 |
0 |
1126 |
0 |
0 |
T14 |
3059 |
0 |
0 |
0 |
T16 |
1760 |
0 |
0 |
0 |
T17 |
1558 |
0 |
0 |
0 |
T18 |
2477 |
1437 |
0 |
0 |
T19 |
1185 |
0 |
0 |
0 |
T20 |
914 |
0 |
0 |
0 |
T21 |
1665 |
0 |
0 |
0 |
T22 |
1140 |
0 |
0 |
0 |
T28 |
0 |
538 |
0 |
0 |
T30 |
0 |
743 |
0 |
0 |
T37 |
0 |
998 |
0 |
0 |
T40 |
0 |
984 |
0 |
0 |
T44 |
0 |
1398 |
0 |
0 |
T45 |
1231 |
0 |
0 |
0 |
T65 |
0 |
1364 |
0 |
0 |
T73 |
0 |
863 |
0 |
0 |
T84 |
0 |
363 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T2,T9,T29 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T9,T29 |
1 | 0 | Covered | T2,T9,T29 |
1 | 1 | Covered | T2,T9,T29 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T9,T29 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T2,T9,T29 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T2,T9,T29 |
1 | 1 | Covered | T2,T9,T29 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T9,T29 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T9,T29 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T9,T29 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T9,T29 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T9,T29 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T76,T132,T133 |
1 | 1 | Covered | T2,T9,T29 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T2,T9,T29 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T2,T9,T29 |
0 |
0 |
1 |
Covered |
T2,T9,T29 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T9,T29 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T9,T29 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
37657 |
0 |
564 |
T2 |
1739 |
1298 |
0 |
1 |
T3 |
223211 |
0 |
0 |
1 |
T4 |
1865 |
0 |
0 |
1 |
T9 |
0 |
1081 |
0 |
0 |
T16 |
1760 |
0 |
0 |
1 |
T18 |
2477 |
0 |
0 |
1 |
T19 |
1185 |
0 |
0 |
1 |
T20 |
914 |
0 |
0 |
1 |
T21 |
1665 |
0 |
0 |
1 |
T22 |
1140 |
0 |
0 |
1 |
T29 |
0 |
1171 |
0 |
0 |
T37 |
0 |
1047 |
0 |
0 |
T38 |
0 |
1035 |
0 |
0 |
T40 |
0 |
1007 |
0 |
0 |
T45 |
1231 |
0 |
0 |
1 |
T76 |
0 |
163 |
0 |
0 |
T77 |
0 |
1427 |
0 |
0 |
T78 |
0 |
1229 |
0 |
0 |
T79 |
0 |
701 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
37657 |
0 |
0 |
T2 |
1739 |
1298 |
0 |
0 |
T3 |
223211 |
0 |
0 |
0 |
T4 |
1865 |
0 |
0 |
0 |
T9 |
0 |
1081 |
0 |
0 |
T16 |
1760 |
0 |
0 |
0 |
T18 |
2477 |
0 |
0 |
0 |
T19 |
1185 |
0 |
0 |
0 |
T20 |
914 |
0 |
0 |
0 |
T21 |
1665 |
0 |
0 |
0 |
T22 |
1140 |
0 |
0 |
0 |
T29 |
0 |
1171 |
0 |
0 |
T37 |
0 |
1047 |
0 |
0 |
T38 |
0 |
1035 |
0 |
0 |
T40 |
0 |
1007 |
0 |
0 |
T45 |
1231 |
0 |
0 |
0 |
T76 |
0 |
163 |
0 |
0 |
T77 |
0 |
1427 |
0 |
0 |
T78 |
0 |
1229 |
0 |
0 |
T79 |
0 |
701 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T11,T30 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T11,T30 |
1 | 0 | Covered | T8,T11,T30 |
1 | 1 | Covered | T8,T11,T30 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T11,T30 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T8,T11,T30 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T8,T11,T30 |
1 | 1 | Covered | T8,T11,T30 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T11,T30 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T11,T30 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T11,T30 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T11,T30 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T8,T11,T30 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T39,T134 |
1 | 1 | Covered | T8,T11,T30 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T8,T11,T30 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T8,T11,T30 |
0 |
0 |
1 |
Covered |
T8,T11,T30 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T8,T11,T30 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T8,T11,T30 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
31450 |
0 |
564 |
T6 |
2294 |
0 |
0 |
1 |
T8 |
2226 |
742 |
0 |
1 |
T11 |
2678 |
1046 |
0 |
1 |
T25 |
146641 |
0 |
0 |
1 |
T30 |
0 |
664 |
0 |
0 |
T39 |
0 |
816 |
0 |
0 |
T40 |
0 |
888 |
0 |
0 |
T41 |
0 |
798 |
0 |
0 |
T55 |
1165 |
0 |
0 |
1 |
T65 |
0 |
1060 |
0 |
0 |
T81 |
0 |
577 |
0 |
0 |
T82 |
0 |
748 |
0 |
0 |
T83 |
0 |
494 |
0 |
0 |
T84 |
745 |
0 |
0 |
1 |
T85 |
1709 |
0 |
0 |
1 |
T86 |
1799 |
0 |
0 |
1 |
T87 |
1105 |
0 |
0 |
1 |
T88 |
10824 |
0 |
0 |
1 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
31450 |
0 |
0 |
T6 |
2294 |
0 |
0 |
0 |
T8 |
2226 |
742 |
0 |
0 |
T11 |
2678 |
1046 |
0 |
0 |
T25 |
146641 |
0 |
0 |
0 |
T30 |
0 |
664 |
0 |
0 |
T39 |
0 |
816 |
0 |
0 |
T40 |
0 |
888 |
0 |
0 |
T41 |
0 |
798 |
0 |
0 |
T55 |
1165 |
0 |
0 |
0 |
T65 |
0 |
1060 |
0 |
0 |
T81 |
0 |
577 |
0 |
0 |
T82 |
0 |
748 |
0 |
0 |
T83 |
0 |
494 |
0 |
0 |
T84 |
745 |
0 |
0 |
0 |
T85 |
1709 |
0 |
0 |
0 |
T86 |
1799 |
0 |
0 |
0 |
T87 |
1105 |
0 |
0 |
0 |
T88 |
10824 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
TOTAL | | 24 | 24 | 100.00 |
ALWAYS | 81 | 7 | 7 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
ALWAYS | 126 | 3 | 3 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
81 |
1 |
1 |
82 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
126 |
1 |
1 |
127 |
1 |
1 |
129 |
1 |
1 |
135 |
1 |
1 |
136 |
1 |
1 |
137 |
1 |
1 |
138 |
1 |
1 |
139 |
1 |
1 |
141 |
1 |
1 |
146 |
1 |
1 |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
Conditions | 42 | 40 | 95.24 |
Logical | 42 | 40 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T31,T33,T42 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T33,T42 |
1 | 0 | Covered | T31,T32,T33 |
1 | 1 | Covered | T31,T33,T42 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T33,T42 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T31,T32,T33 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T31,T32,T33 |
1 | 1 | Covered | T31,T32,T33 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T31,T32,T33 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T31,T32,T33 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T135,T136 |
1 | 1 | Covered | T31,T32,T33 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
-1- | Status | Tests |
0 | Covered | T31,T32,T33 |
1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
TERNARY |
141 |
4 |
4 |
100.00 |
TERNARY |
146 |
3 |
3 |
100.00 |
TERNARY |
150 |
3 |
3 |
100.00 |
IF |
81 |
2 |
2 |
100.00 |
IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T31,T32,T33 |
0 |
0 |
1 |
Covered |
T31,T32,T33 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T31,T32,T33 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T31,T32,T33 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
27923 |
0 |
564 |
T31 |
1686 |
970 |
0 |
1 |
T32 |
1980 |
1144 |
0 |
1 |
T33 |
0 |
1174 |
0 |
0 |
T42 |
0 |
1050 |
0 |
0 |
T43 |
0 |
771 |
0 |
0 |
T44 |
0 |
1019 |
0 |
0 |
T64 |
2120 |
0 |
0 |
1 |
T65 |
2263 |
0 |
0 |
1 |
T69 |
849 |
0 |
0 |
1 |
T79 |
863 |
0 |
0 |
1 |
T83 |
1345 |
0 |
0 |
1 |
T92 |
0 |
1193 |
0 |
0 |
T93 |
0 |
1226 |
0 |
0 |
T96 |
1206 |
0 |
0 |
1 |
T97 |
1551 |
0 |
0 |
1 |
T98 |
1410 |
0 |
0 |
1 |
T137 |
0 |
1075 |
0 |
0 |
T138 |
0 |
736 |
0 |
0 |
ValidOPairedWithReadyI_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
192773565 |
27923 |
0 |
0 |
T31 |
1686 |
970 |
0 |
0 |
T32 |
1980 |
1144 |
0 |
0 |
T33 |
0 |
1174 |
0 |
0 |
T42 |
0 |
1050 |
0 |
0 |
T43 |
0 |
771 |
0 |
0 |
T44 |
0 |
1019 |
0 |
0 |
T64 |
2120 |
0 |
0 |
0 |
T65 |
2263 |
0 |
0 |
0 |
T69 |
849 |
0 |
0 |
0 |
T79 |
863 |
0 |
0 |
0 |
T83 |
1345 |
0 |
0 |
0 |
T92 |
0 |
1193 |
0 |
0 |
T93 |
0 |
1226 |
0 |
0 |
T96 |
1206 |
0 |
0 |
0 |
T97 |
1551 |
0 |
0 |
0 |
T98 |
1410 |
0 |
0 |
0 |
T137 |
0 |
1075 |
0 |
0 |
T138 |
0 |
736 |
0 |
0 |