SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_edn_core.u_prim_mubi4_sync_edn_enable | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_cmd_fifo_rst | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_auto_req_mode | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_edn_core.u_prim_mubi4_sync_boot_req_mode | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
95.31 | 100.00 | 85.94 | 100.00 | u_edn_core |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 24 | 24 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 23 | 23 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 2256 | 2256 | 0 | 0 |
OutputsKnown_A | 771094260 | 770620192 | 0 | 0 |
gen_no_flops.OutputDelay_A | 771094260 | 770620192 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2256 | 2256 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T4 | 4 | 4 | 0 | 0 |
T16 | 4 | 4 | 0 | 0 |
T18 | 4 | 4 | 0 | 0 |
T19 | 4 | 4 | 0 | 0 |
T20 | 4 | 4 | 0 | 0 |
T21 | 4 | 4 | 0 | 0 |
T22 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 771094260 | 770620192 | 0 | 0 |
T1 | 7800 | 7136 | 0 | 0 |
T2 | 6956 | 6644 | 0 | 0 |
T3 | 892844 | 892796 | 0 | 0 |
T4 | 7460 | 6760 | 0 | 0 |
T16 | 7040 | 6796 | 0 | 0 |
T18 | 9908 | 9536 | 0 | 0 |
T19 | 4740 | 4432 | 0 | 0 |
T20 | 3656 | 3456 | 0 | 0 |
T21 | 6660 | 6444 | 0 | 0 |
T22 | 4560 | 3904 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 771094260 | 770620192 | 0 | 0 |
T1 | 7800 | 7136 | 0 | 0 |
T2 | 6956 | 6644 | 0 | 0 |
T3 | 892844 | 892796 | 0 | 0 |
T4 | 7460 | 6760 | 0 | 0 |
T16 | 7040 | 6796 | 0 | 0 |
T18 | 9908 | 9536 | 0 | 0 |
T19 | 4740 | 4432 | 0 | 0 |
T20 | 3656 | 3456 | 0 | 0 |
T21 | 6660 | 6444 | 0 | 0 |
T22 | 4560 | 3904 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 24 | 24 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 23 | 23 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 564 | 564 | 0 | 0 |
OutputsKnown_A | 192773565 | 192655048 | 0 | 0 |
gen_no_flops.OutputDelay_A | 192773565 | 192655048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 564 | 564 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 564 | 564 | 0 | 0 |
OutputsKnown_A | 192773565 | 192655048 | 0 | 0 |
gen_no_flops.OutputDelay_A | 192773565 | 192655048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 564 | 564 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 564 | 564 | 0 | 0 |
OutputsKnown_A | 192773565 | 192655048 | 0 | 0 |
gen_no_flops.OutputDelay_A | 192773565 | 192655048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 564 | 564 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 564 | 564 | 0 | 0 |
OutputsKnown_A | 192773565 | 192655048 | 0 | 0 |
gen_no_flops.OutputDelay_A | 192773565 | 192655048 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 564 | 564 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 192773565 | 192655048 | 0 | 0 |
T1 | 1950 | 1784 | 0 | 0 |
T2 | 1739 | 1661 | 0 | 0 |
T3 | 223211 | 223199 | 0 | 0 |
T4 | 1865 | 1690 | 0 | 0 |
T16 | 1760 | 1699 | 0 | 0 |
T18 | 2477 | 2384 | 0 | 0 |
T19 | 1185 | 1108 | 0 | 0 |
T20 | 914 | 864 | 0 | 0 |
T21 | 1665 | 1611 | 0 | 0 |
T22 | 1140 | 976 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |