Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
75.76	75.76	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	75.76	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.76	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	8	13	61.90

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	8	13	61.90	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	64	1			T33	1		T43	1		T93	1
auto_req_mode	63	1			T6	1		T10	1		T29	1
sw_mode	2761	1			T2	19		T17	58		T19	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

110

1

T6

1

T10

1

T29

1

single

38

1

T33

1

T43

1

T8

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1232	1			T19	1		T6	1		T10	1
auto[2]	63	1			T262	1		T263	51		T264	2
auto[3]	180	1			T17	58		T52	9		T265	1
auto[4]	65	1			T21	7		T51	5		T266	7
auto[5]	174	1			T156	8		T267	64		T268	1
auto[6]	161	1			T20	77		T67	1		T269	82
auto[7]	1013	1			T2	19		T53	38		T7	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	8	13	61.90	8

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[2]]	[boot_req_mode]	0	1	1
[auto[3]]	[boot_req_mode , auto_req_mode]	--	--	2
[auto[4]]	[auto_req_mode]	0	1	1
[auto[5] - auto[6]]	[boot_req_mode , auto_req_mode]	--	--	4

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	55	1			T33	1		T43	1		T93	1
auto[1]	auto_req_mode	54	1			T6	1		T10	1		T29	1
auto[1]	sw_mode	1123	1			T19	1		T92	43		T65	1
auto[2]	auto_req_mode	1	1			T262	1		-	-		-	-
auto[2]	sw_mode	62	1			T263	51		T264	2		T270	1
auto[3]	sw_mode	180	1			T17	58		T52	9		T265	1
auto[4]	boot_req_mode	1	1			T94	1		-	-		-	-
auto[4]	sw_mode	64	1			T21	7		T51	5		T266	7
auto[5]	sw_mode	174	1			T156	8		T267	64		T268	1
auto[6]	sw_mode	161	1			T20	77		T67	1		T269	82
auto[7]	boot_req_mode	8	1			T36	1		T39	1		T41	1
auto[7]	auto_req_mode	8	1			T7	1		T9	1		T38	1
auto[7]	sw_mode	997	1			T2	19		T53	38		T66	6