Summary for Variable cp_clen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_clen
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
some_cmd_data |
2556 |
1 |
|
|
T2 |
11 |
|
T3 |
4 |
|
T17 |
54 |
no_cmd_data |
647 |
1 |
|
|
T2 |
3 |
|
T17 |
14 |
|
T20 |
23 |
Summary for Variable cp_flags
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_flags
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
true |
1622 |
1 |
|
|
T2 |
10 |
|
T3 |
2 |
|
T17 |
30 |
false |
1581 |
1 |
|
|
T2 |
4 |
|
T3 |
2 |
|
T17 |
38 |
Summary for Variable cp_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_glen
Excluded/Illegal bins
NAME | COUNT | STATUS |
zero |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
multiple |
1375 |
1 |
|
|
T2 |
7 |
|
T3 |
2 |
|
T17 |
23 |
one |
187 |
1 |
|
|
T3 |
2 |
|
T6 |
2 |
|
T4 |
2 |
Summary for Cross cr_clen_flags_glen
Samples crossed: cp_clen cp_flags cp_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cr_clen_flags_glen
Bins
cp_clen | cp_flags | cp_glen | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
some_cmd_data |
true |
multiple |
542 |
1 |
|
|
T2 |
5 |
|
T3 |
1 |
|
T17 |
7 |
some_cmd_data |
true |
one |
75 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T10 |
2 |
some_cmd_data |
false |
multiple |
552 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
13 |
some_cmd_data |
false |
one |
78 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T29 |
2 |
no_cmd_data |
true |
multiple |
145 |
1 |
|
|
T2 |
1 |
|
T17 |
1 |
|
T20 |
7 |
no_cmd_data |
true |
one |
20 |
1 |
|
|
T4 |
1 |
|
T5 |
1 |
|
T107 |
1 |
no_cmd_data |
false |
multiple |
136 |
1 |
|
|
T17 |
2 |
|
T20 |
7 |
|
T52 |
1 |
no_cmd_data |
false |
one |
14 |
1 |
|
|
T4 |
1 |
|
T28 |
1 |
|
T44 |
1 |