Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	0	40	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	0	40	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	1544	1			T2	6		T17	30		T20	39
non_zero_bins[1]	1016	1			T2	5		T17	24		T20	22
zero	6858	1			T1	2		T2	46		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	2762	1			T2	19		T17	58		T19	1
gen	3304	1			T1	1		T2	19		T17	58
res	203	1			T6	3		T10	3		T29	4
ins	3149	1			T1	1		T2	19		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

6760

1

T1

2

T2

41

T3

1

mubi_true

2658

1

T2

16

T17

41

T19

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

4739

1

T1

2

T2

29

T17

90

pass

4679

1

T2

28

T3

1

T17

84

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	0	40	100.00
Automatically Generated Cross Bins	40	0	40	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	1058	1			T2	6		T17	21		T20	24
uni	zero	fail	mubi_true	347	1			T2	4		T17	5		T19	1
uni	zero	pass	mubi_false	1007	1			T2	7		T17	26		T20	31
uni	zero	pass	mubi_true	350	1			T2	2		T17	6		T20	15
gen	non_zero_bins[0]	fail	mubi_false	195	1			T17	5		T20	7		T52	1
gen	non_zero_bins[0]	fail	mubi_true	193	1			T2	1		T17	3		T20	2
gen	non_zero_bins[0]	pass	mubi_false	176	1			T17	4		T20	6		T21	1
gen	non_zero_bins[0]	pass	mubi_true	197	1			T2	2		T17	4		T20	8
gen	non_zero_bins[1]	fail	mubi_false	114	1			T17	3		T20	5		T51	2
gen	non_zero_bins[1]	fail	mubi_true	150	1			T17	2		T20	1		T10	1
gen	non_zero_bins[1]	pass	mubi_false	117	1			T2	2		T17	2		T20	2
gen	non_zero_bins[1]	pass	mubi_true	127	1			T17	2		T20	3		T51	1
gen	zero	fail	mubi_false	849	1			T1	1		T2	9		T17	13
gen	zero	fail	mubi_true	176	1			T17	4		T21	1		T33	1
gen	zero	pass	mubi_false	846	1			T2	4		T17	14		T20	21
gen	zero	pass	mubi_true	164	1			T2	1		T17	2		T20	2
res	non_zero_bins[0]	fail	mubi_false	13	1			T6	1		T10	1		T76	1
res	non_zero_bins[0]	fail	mubi_true	32	1			T7	2		T27	3		T28	3
res	non_zero_bins[0]	pass	mubi_false	13	1			T10	2		T76	1		T44	1
res	non_zero_bins[0]	pass	mubi_true	25	1			T27	2		T9	1		T277	1
res	non_zero_bins[1]	fail	mubi_false	23	1			T8	1		T31	1		T103	1
res	non_zero_bins[1]	fail	mubi_true	16	1			T6	1		T107	2		T37	2
res	non_zero_bins[1]	pass	mubi_false	15	1			T8	1		T31	1		T103	1
res	non_zero_bins[1]	pass	mubi_true	15	1			T6	1		T26	3		T107	1
res	zero	fail	mubi_false	14	1			T32	1		T82	2		T277	1
res	zero	fail	mubi_true	9	1			T29	1		T100	1		T88	3
res	zero	pass	mubi_false	12	1			T44	1		T32	2		T38	1
res	zero	pass	mubi_true	16	1			T29	3		T100	2		T278	2
ins	non_zero_bins[0]	fail	mubi_false	175	1			T17	8		T20	6		T21	1
ins	non_zero_bins[0]	fail	mubi_true	172	1			T2	1		T17	1		T20	3
ins	non_zero_bins[0]	pass	mubi_false	179	1			T17	3		T20	3		T6	1
ins	non_zero_bins[0]	pass	mubi_true	174	1			T2	2		T17	2		T20	4
ins	non_zero_bins[1]	fail	mubi_false	106	1			T17	4		T51	1		T10	1
ins	non_zero_bins[1]	fail	mubi_true	113	1			T2	1		T17	4		T20	3
ins	non_zero_bins[1]	pass	mubi_false	120	1			T2	1		T17	3		T52	1
ins	non_zero_bins[1]	pass	mubi_true	100	1			T2	1		T17	4		T20	8
ins	zero	fail	mubi_false	840	1			T1	1		T2	7		T17	17
ins	zero	fail	mubi_true	144	1			T20	5		T7	1		T13	1
ins	zero	pass	mubi_false	888	1			T2	5		T3	1		T17	10
ins	zero	pass	mubi_true	138	1			T2	1		T17	2		T20	3

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded